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Simulators >> AMS Simulators >> ÷ (NP+S) divider not working
https://designers-guide.org/forum/YaBB.pl?num=1427091881

Message started by cktdesigner on Mar 22^nd, 2015, 11:24pm

Title: ÷ (NP+S) divider not working
Post by cktdesigner on Mar 22^nd, 2015, 11:24pm

Hi,

I am trying to verify the function of a NP+S divider.

I am referring to the divider from Razavi's book shown in the attachment.

In my test-bench all blocks in this NP+S divider are models and no transistor level implementations are present.

In the next few posts, I show schematic of the:
1. NP+S divider
2. test bench
3. ÷2 OR 3 dual-modulus prescaler.

along with the veriloga code for the blocks which I used from this website.

The simulator used is AMS simulator and Virtuoso is IC615.

Now, I will describe the problem I am facing.

In the test-bench the frequency of the input has been set at 14MHz and P has been set to 5 and S has been set to 4.

which => NP+S = 2x5 + 4 = 14

N is 2 since there is a ÷2OR3 dual-modulus prescaler being used.

So the divider as a whole must provide a divide ratio of 14 and hence the frequency of the output of the divider must be 1MHz.

The problem is that the frequency of the output is not at 1MHz but at 1.08MHz which is incorrect.

This NP+S divider does not seem to function correctly.

Please note that I have INDIVIDUALLY checked the functionality of the ÷2OR3 dual-modulus prescaler, ÷P program counter (PC) and the ÷S swallow counter.

All 3 seem to function properly when checked in a stand-alone mode.

I searched extensively about this divider over the web and this forum as well but could not come up with the root cause for the problem, yet.

Could some one please help point out the reason why this NP+S divider is not working?

Title: Re: ÷ (NP+S) divider not working
Post by cktdesigner on Mar 22^nd, 2015, 11:27pm

Schematic of the NP+S divider is attached.

Title: Re: ÷ (NP+S) divider not working
Post by cktdesigner on Mar 22^nd, 2015, 11:29pm

Schematic of the test-bench

Title: Re: ÷ (NP+S) divider not working
Post by cktdesigner on Mar 22^nd, 2015, 11:41pm

Schematic of the ÷2OR3 dual-modulus prescaler along with code for each of the blocks.

This dual-modulus prescaler is taken from Razavi's RF Microelectronics 2nd Edition (p.679, Fig.10.31, Chapter 10, Sec 10.6).

Please note that when MC=0 the circuit divides by 3 and when MC=1 the circuit divides by 2.

code for DFF:
`include "constants.vams"
`include "disciplines.vams"

module adff (q, qb, clk, d);

output q; voltage q; // Q output
output qb; voltage qb; // Q bar output
input clk; voltage clk; // Clock input (edge triggered)
input d; voltage d; // D input

real td;
real tt;
real vh;
real vl;
real vth;
integer dir;

real state;

analog begin

td = 0;
tt = 1p;
vh = 1;
vl = 0;
vth = (vh + vl)/2;
dir = +1;

@(cross(V(clk) - vth, dir))
state = (V(d) > vth);

V(q) <+ transition( state ? vh : vl, td, tt );

V(qb) <+ transition( state ? vl : vh, td, tt );

end
endmodule

Code for OR Gate:
`include "constants.vams"
`include "disciplines.vams"

module aor (out, in1, in2);

output out; voltage out;
input in1, in2; voltage in1, in2;
real vh; // output voltage in high state
real vl; // output voltage in low state
real vth; // threshold voltage at inputs
real td; // delay to start of output transition
real tt; // transition time of output signals

analog begin
vh = 1;
vl = 0;
vth = (vh + vl)/2;
td = 0;
tt = 1p;
@(cross(V(in1) - vth) or cross(V(in2) - vth))
;

V(out) <+ transition( ((V(in1) > vth) || (V(in2) > vth)) ? vh : vl, td, tt );
end
endmodule

Code for AND Gate:
`include "constants.vams"
`include "disciplines.vams"

module aand (out, in1, in2);

output out; voltage out;
input in1, in2; voltage in1, in2;
real vh; // output voltage in high state
real vl; // output voltage in low state
real vth; // threshold voltage at inputs
real td; // delay to start of output transition
real tt; // transition time of output signals

analog begin
vh = 1;
vl = 0;
vth = (vh + vl)/2;
td = 0;
tt = 1p;
@(cross(V(in1) - vth) or cross(V(in2) - vth))
;

V(out) <+ transition( ((V(in1) > vth) && (V(in2) > vth)) ? vh : vl, td, tt );
end
endmodule

The NOT gate in the schematic is realized as a NAND gate with both inputs tied together. The code for the NAND gate inside the NOT gate module in the schematic is shown below

Code for NAND gate:
`include "constants.vams"
`include "disciplines.vams"

module anand (out, in1, in2);

output out; voltage out;
input in1, in2; voltage in1, in2;
real vh; // output voltage in high state
real vl; // output voltage in low state
real vth; // threshold voltage at inputs
real td; // delay to start of output transition
real tt; // transition time of output signals

analog begin
vh = 1;
vl = 0;
vth = (vh + vl)/2;
td = 0;
tt = 1p;
@(cross(V(in1) - vth) or cross(V(in2) - vth))
;
V(out) <+ transition( !((V(in1) > vth) && (V(in2) > vth)) ? vh : vl, td, tt );
end
endmodule

Title: Re: ÷ (NP+S) divider not working
Post by cktdesigner on Mar 22^nd, 2015, 11:47pm

Please note that for the ÷P Program Counter the value of "P" is taken as an input DC voltage. (this is temporary just for convenience of use).

Code for the ÷P Program Counter:

`include "constants.vams"
`include "disciplines.vams"

module divider2 (out, in, div);

output out; voltage out; // output
input in; voltage in; // input (edge triggered)
input div; voltage div; // div (div ratio input)
real vh; // output voltage in high state
real vl; // output voltage in low state
real vth; // threshold voltage at input

integer dir; // dir=1 for positive edge trigger
// dir=-1 for negative edge trigger

real tt; // transition time of output signal
real td; // average delay from input to output
integer count, n;

analog begin
vh=+1;
vl=0;
vth=(vh+vl)/2;
dir=1;
tt=1p;
td=0;

@(cross(V(in) - vth, dir))
begin
count = count + 1; // count input transitions
if (count >= V(div))
count = 0;
n = (2*count >= V(div));
end
V(out) <+ transition(n ? vh : vl, td, tt);

end
endmodule

Title: Re: ÷ (NP+S) divider not working
Post by cktdesigner on Mar 22^nd, 2015, 11:49pm

Please note that for the ÷S Swallow Counter the value of "S" is taken as an input DC voltage. (this is temporary just for convenience of use).

Code for the ÷S Swallow Counter:

`include "constants.vams"
`include "disciplines.vams"

module sw_cntr (out, in, div, rst);

output out; voltage out; // output
input in; voltage in; // input (edge triggered)
input div; voltage div; // div (div ratio input)
input rst; voltage rst; //rst (RESET input)

real vh; // output voltage in high state
real vl; // output voltage in low state
real vth; // threshold voltage at input

integer dir; // dir=1 for positive edge trigger
// dir=-1 for negative edge trigger

real tt; // transition time of output signal
real td; // average delay from input to output
integer count, n;

analog begin
vh=+1;
vl=0;
vth=(vh+vl)/2;
dir=1;
tt=1p;
td=1p;

@(cross(V(in) - vth, dir))
begin
count=count+1;
if ((count >= V(div)))
count = 0;
n = (2*count >= V(div));
end

@(cross(V(rst) - vth, dir))
begin
count = 0; // reset count on rising edge of rst pin
n = 0;
end

V(out) <+ transition(n ? vh : vl, td, tt);
end
endmodule

Title: Re: ÷ (NP+S) divider not working
Post by cktdesigner on Mar 22^nd, 2015, 11:52pm

Finally here are the actual transient plots for some of the relevant signals of interest.

Note that frequency of output signal is 1.08MHz and not at 1MHz.

I would also like to mention that I have placed the cursors (Both baseline and markerA) extremely accurately right on the rising edges. So the frequency of the output (i.e. pout) is exactly @ 1.08MHz. There is no question of inaccuracy in measurement here.

Title: Re: ÷ (NP+S) divider not working
Post by Geoffrey_Coram on Mar 26^th, 2015, 7:02am

Please update this post after you've applied Ken's suggestions from your other thread ( http://www.designers-guide.org/Forum/YaBB.pl?num=1426479908 )

Title: Re: ÷ (NP+S) divider not working
Post by cktdesigner on Mar 26^th, 2015, 8:52am

Geoffrey_Coram wrote on Mar 26^th, 2015, 7:02am:

Please update this post after you've applied Ken's suggestions from your other thread ( http://www.designers-guide.org/Forum/YaBB.pl?num=1426479908 )

Hi Geoffrey,

I have already incorporated Ken's suggestion of making tt finite and non-zero. If you carefully note tt has been set to 1psec.

cktdesigner

Title: Re: ÷ (NP+S) divider not working
Post by Ken Kundert on Mar 26^th, 2015, 9:02am

I recommended that the transition time be nonzero, and that seems to be the case in these models. However, setting tt and td to 1ps will just force the simulator to use small time steps for no purpose, resulting in slow simulations. You should always set td to zero unless you need it, and make tt as large as practical. In this example there seems to be no reason that it should be smaller than 1ns, and could be 10ns or more.

To a simulator, a time point is a 'unit of work'. Change the settings in your waveform views so that it shows the actual time points used by the simulator, then play with you tt settings without changing the period of the underlying signal and see how your choices affect the number of 'units of work' that are needed to render a single edge.

-Ken

Title: Re: ÷ (NP+S) divider not working
Post by cktdesigner on Mar 26^th, 2015, 9:27am

Ken Kundert wrote on Mar 26^th, 2015, 9:02am:

Hi Ken,

I actually need to set the input frequency to 2.4GHz. I need to use this divider in a 2.4GHz PLL. This is the reason I set tt to 1ps and td to 0.

For ease of explanation of my problem I chose small values of Fin=14MHz, P=5 and S=4.

My point is that this divider which seems to be a standard circuit and taken out of a popular book does NOT work.

I just wonder how can such a standard circuit given in such a popular book not work?

I am confident that the models are coded correctly. They seem to function correctly on a standalone basis. So, where is the problem?

I thought there are many experts here in dividers and they could easily point out the reason for the incorrect functioning of the divider.

cktdesigner

Title: Re: ÷ (NP+S) divider not working
Post by Geoffrey_Coram on Apr 13^th, 2015, 10:34am

cktdesigner wrote on Mar 26^th, 2015, 9:27am:

I thought there are many experts here in dividers and they could easily point out the reason for the incorrect functioning of the divider.

I'm not an expert in dividers, but I think they would have the same problem I do: there are a lot of ways you could have introduced a small mistake in the circuit or simulation, and I'm not sure how to verify it without reproducing all your work.

I noticed that your circuit does divide by 13, so I wonder if you try other values of NP+S, do you always get a divide ratio of NP+(S-1), or always NP+3, or something else? If you do get NP+(S-1), would that point you to the circuit element that is not performing correctly?