The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Could you explain the meaning of a verilog-AMS code?
https://designers-guide.org/forum/YaBB.pl?num=1427513986

Message started by ruwan2 on Mar 27^th, 2015, 8:39pm

Title: Could you explain the meaning of a verilog-AMS code?
Post by ruwan2 on Mar 27^th, 2015, 8:39pm

Hi,

I come across the following code from verilog-AMS reference book. First of
all, it is found that I have to comment out one of

// wire dnet;

or

// ddiscrete dnet;

in order a verilog-AMS simulation software (SMASH) to work.

What is the meaning of the above two attributes?

It has:

electrical anet;

'dnet' has obvious electrical attribute? I feel that it is weird to have

'electrical anet;'

Could you explain it to me?

Thanks,

module a2d(dnet, anet);
input dnet;
output anet;
wire dnet;
ddiscrete dnet;
electrical anet;
real avar;
analog begin
if (dnet === 1'b1)
avar = 5;
else if (dnet === 1'bx)
avar = avar; // hold value
else if (dnet === 1'b0)
avar = 0;
else if (dnet === 1'bz)
avar = 2.5; // high impedance - float value
V(anet) <+ avar;
end
endmodule

Title: Re: Could you explain the meaning of a verilog-AMS code?
Post by Geoffrey_Coram on Mar 30^th, 2015, 6:10am

Shouldn't this be "module d2a" ?

It looks to me to be reading the values from the digital net "dnet" and setting the (analog) value on "anet"

You should really read Section 3.6.2.2, Domain binding, from VAMS LRM 2.4, which gives as examples the disciplines "electrical" and "ddiscrete"