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Design Languages >> Verilog-AMS >> how to use "mixedsignal;"
https://designers-guide.org/forum/YaBB.pl?num=1427607170

Message started by ruwan2 on Mar 28^th, 2015, 10:32pm

Title: how to use "mixedsignal;"
Post by ruwan2 on Mar 28^th, 2015, 10:32pm

Hi,

I see the following code on LRM. I do not see "mixedsignal" defined. Whether "mixedsignal" is a reserved word?

Could you explain it to me?

Thanks,

Code:

module dig_inv(in, out);
input in;
output out;
reg out;
ddiscrete in, out;
always begin
out = #10 ~in;
end
endmodule
module analog_inv(in, out);
input in;
output out;
electrical in, out;
parameter real vth = 2.5;
real outval;
analog begin
if (V(in) > vth)
outval = 0;
else
outval = 5 ;
V(out) <+ transition(outval);
end
endmodule
module ring;
dig_inv d1 (n1, n2);
dig_inv d2 (n2, n3);
analog_inv a3 (n3, n1);
endmodule
connectmodule elect_to_logic(el,cm);
input el;
output cm;
reg cm;
electrical el;
ddiscrete cm;
always
@(cross(V(el) - 2.5, 1))
cm = 1;
always
@(cross(V(el) - 2.5, -1))
cm = 0;
endmodule
connectmodule logic_to_elect(cm,el);
input cm;
output el;
ddiscrete cm;
electrical el;
analog
V(el) <+ transition((cm == 1) ? 5.0 : 0.0);
endmodule
connectrules mixedsignal;
connect elect_to_logic;
connect logic_to_elect;
endconnectrules

Title: Re: how to use "mixedsignal;"
Post by Ken Kundert on Mar 30^th, 2015, 11:57am

You are defining the name mixedsignal. It should be included as a top-level module when running the simulation so that verilog knows which connect modules to use.

When asking for help, you should make it easier for people to help you by formatting your code so that it is readable. The lack of indenting in your code makes it unnecessarily difficult to read.

-Ken