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Design Languages >> Verilog-AMS >> Why current through the resistor changing
https://designers-guide.org/forum/YaBB.pl?num=1427898710

Message started by ruwan2 on Apr 1^st, 2015, 7:31am

Title: Why current through the resistor changing
Post by ruwan2 on Apr 1^st, 2015, 7:31am

Hi,

I simulate the following code with SMASH.

Code:

`timescale 100ps / 1ps
`include "disciplines.vams"

module testbench ();
electrical gnd;
ground gnd;

reg clk;
initial clk=0;
wire b;
wire out1;

always begin
#10
clk=1;
#10
clk=0;
#10
clk=1'bx;
#10
clk=0;
#10
clk=1'bz;
end

buffer buf0 (b, clk);
resistor #(.r(100k)) r0 (b, gnd);
// sinVarFreq svf0 (out1, gnd);
endmodule

module buffer (out, in);
output out;
input in;

assign out = in;
endmodule

I get the transient of the logic and resister current as in the picture:

The current through the resistor from 0 increasing to larger, although the voltage I think changes in the same way with time. How to understand the current curve?

Thanks,

Title: Re: Why current through the resistor changing
Post by Ken Kundert on Apr 1^st, 2015, 11:14am

You are concerned about a 2 zepto Ampere current? That is 9 orders of magnitude smaller than iabstol.

It seems to me that rather than being concerned about "Why [is the] current through the resistor changing", you might ask the question "Why isn't the current through the resistor changing". It does not seem like your resistor is being driven at all.

-Ken

Title: Re: Why current through the resistor changing
Post by ruwan2 on Apr 1^st, 2015, 12:43pm

Thank AMS expert. You exclude me one direction.
Yes, my next question is why the digital buffer does not drive the resistor? It needs a d2a module to adapter between them?

Title: Re: Why current through the resistor changing
Post by Ken Kundert on Apr 1^st, 2015, 1:46pm

Yes, a connect module is needed. The simulator should have inserted one, or complained if it could not. It might also be that a connect module was inserted, but the connect module was not configured properly.

-Ken

Title: Re: Why current through the resistor changing
Post by ruwan2 on Apr 2^nd, 2015, 6:12am

Hi,

After several trials with the example, I am still puzzled about the resistor in the module. I have tested input value to resistor. It is found that it only accepts logic '1' or '0'. The current does change when there is one '1' at one of the two pins, but wire b logic does not show impact on the current.

In the following code,

Code:

module testbench ();
electrical gnd;
ground gnd;

reg clk;
initial clk=0;
wire b;
wire out1;

always begin
#100
clk=1;
#100
clk=0;
#10
clk=1'bx;
#100
clk=0;
#10
clk=1'bz;
end

buffer buf0 (b, clk);
resistor #(.r(10)) r0 (b, 1);
endmodule

The current image is as below:

http://i58.tinypic.com/2jdjgvt.png

I cannot figure out how the vertical axis values come out. Its maxim is Ampere?

When a number, such as '19' instead of '1' or '0' input, there is the following error message:

ERROR: instantiation of SPICE primitive 'resistor' failed (instance and model do not match: cannot connect a non-signal to the SPICE port 'SPICE Port', except "1'b1", "1'b0", "1" and "0"; actual expression has to be either a concatenation, or a part select or an bit select made of signals)

Although wire b has logic '1' and '0', it does not change the resistor current in the image.

Could you explain it to me?

Thanks,

Title: Re: Why current through the resistor changing
Post by ruwan2 on Apr 2^nd, 2015, 6:34am

Here is a direct link to the image:

Title: Re: Why current through the resistor changing
Post by Ken Kundert on Apr 2^nd, 2015, 10:44am

No, I have never used Smash.

It is odd that you never plot the voltage, nor have you given any indication that you have provided a mapping from logic value to voltage levels.

-Ken