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Design >> RF Design >> Swing in VCO
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Message started by Rakesh on Apr 1^st, 2015, 10:12am

Title: Swing in VCO
Post by Rakesh on Apr 1^st, 2015, 10:12am

Hi,
I designed a class D VC0. The swing across my core transistors is 4V whereas the DC operating point is only 1V. The nominal voltage is 1.2V in this technology. SO I was wondering whether the transistors will break down if the ac swing is 4V at 5Ghz between gate and drain. I do see a warning that the oxide breakdown is 6V when I run cadence.

Thanks
Rakesh

Title: Re: Swing in VCO
Post by aaron_do on Apr 1^st, 2015, 10:28pm

Hi Rakesh,

the short answer is yes.

As I recall, if you have 1.2-V technology, then your oxide can sustain 1.2-V DC + about 10%, but you shouldn't use a supply voltage more than 1.2 V. You can look up the TDDB (time dependent dielectric breakdown) specs for the process, and you will see that the mean time to failure reduces exponentially with voltage. In your case, this time to failure can approximately be multiplied by the duty cycle. i.e. if you duty cycle is 20%, then the oxide will last 5x longer, but remember that as the time to failure reduces exponentially with voltage but only linearly with time, a 1/5 duty cycle has nowhere near the impact as 5x voltage.

Note that there are some papers which claim that at RF, transistors can sustain much larger AC swings. I don't recall which papers they are, and I don't think manufacturers normally check the transistors against large RF AC voltage swings, so try it at your own risk. IMO 4 V seems way too large for a 1.2-V transistor.

In your case, you can consider using the I/O transistors. Also, have a look at class-E PA papers to see what techniques they use to meet reliability requirements.

Aaron