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Design Languages >> Verilog-AMS >> Question about two branches for a diode model
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Message started by ruwan2 on Apr 10^th, 2015, 7:20am

Title: Question about two branches for a diode model
Post by ruwan2 on Apr 10^th, 2015, 7:20am

Hi,

When I read the following example on AMS, I am puzzled about two branches for two terminals. What relationship of these two branches i_diode, junc_cap ? A diode should have one current flow through, what about the two current?

Thanks

Code:

module diode (a, c);
electrical a, c;
branch (a, c) i_diode, junc_cap;
parameter real is = 1e-14, tf = 0, cjo = 0, imax = 1, phi = 0.7 ;
analog begin
I(i_diode) <+ is*(limexp(V(i_diode)/$vt) – 1);
I(junc_cap) <+
ddt(tf*I(i_diode) - 2*cjo*sqrt(phi*(phi*V(junc_cap))));
if (I(<a>) > imax)
$strobe( "Warning: diode is melting!" );
end
endmodule

Title: Re: Question about two branches for a diode model
Post by ruwan2 on Apr 10^th, 2015, 8:08am

Excuse me. I understand now. The capacitor is parallel with the diode. Thanks