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Design Languages >> Verilog-AMS >> What behavior is it when there is no analog/digital conversion module?
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Message started by ruwan2 on Apr 13^th, 2015, 7:04am

Title: What behavior is it when there is no analog/digital conversion module?
Post by ruwan2 on Apr 13^th, 2015, 7:04am

Hi,
I am using a non-mainstream EDA tool on AMS learning. It looks like it ignores analog and digital conversion modules. From its example project, it supports analog and digital mixed signals by putting analog component out of verilog file into a SPICE like netlist file. If I put a resistor inside a verilog-AMS file with some logic gates, there is no current flow through the resistor.
So, it looks like its digital circuit works with the analog circuit with only input threshold taking care of, in separate file and categories (logic: verilog; analog: SPICE net file). The digital timing is controlled by 'timescale parameter. It is different from AMS LRM connectmodule requirement (analog component can be inside a AMS file).

I would ask you that whether those a2d d2a rule conversion modules are necessary in your EDA tools?

Thanks,