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Analog Verification >> Analog Performance Verification >> ADC DNL INL simulation using adc_dnl_8bit
https://designers-guide.org/forum/YaBB.pl?num=1429153674

Message started by kane on Apr 15^th, 2015, 8:07pm

Title: ADC DNL INL simulation using adc_dnl_8bit
Post by kane on Apr 15^th, 2015, 8:07pm

I am designing SAR ADC and want to use "adc_dnl_8bit" block to get the DNL of the ADC. But I found the amplitude of the "vclk" is too small. 1. how to solve this problem? 2. where to get the DNL value ?

Title: Re: ADC DNL INL simulation using adc_dnl_8bit
Post by weber8722 on Apr 21^st, 2015, 11:36pm

Hi,

isnt there a parameter to enter the clk amplitude? Use Edit Property, then swtich the cyclic field to "veriloga" to see all parameters.
If this is still a problem use e.g. an vcvs from analogLib as little amplitfier. This is also needed for differential circuits.

Bye Stephan