The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> variabe capacitor in hspice
https://designers-guide.org/forum/YaBB.pl?num=1431377936

Message started by vahid on May 11^th, 2015, 1:58pm

Title: variabe capacitor in hspice
Post by vahid on May 11^th, 2015, 1:58pm

hi i decide simulate this circuit in hspice but i can't modeling variable capacitor section the capacitors in this circuit change by move (capacitive accelerometer ) and Unfortunately i have no Enough information about veriloge if I understand correctly , i can use veriloge in hspice

if you can write variable capacitor in verivlog i thank you verrrry much

Title: Re: variabe capacitor in hspice
Post by Geoffrey_Coram on May 12^th, 2015, 10:40am

How do you plan to simulate the motion of the cap plates?

Verilog-A can support multi-physics simulations, where the position, velocity, and acceleration of the plates are unknowns of the system, and then the position is used to determine the capacitance. I think you probably want to go this route, but if you don't know what I'm talking about, you have some reading to do before you're ready for the next step.

Title: Re: variabe capacitor in hspice
Post by vahid on May 12^th, 2015, 11:38am

yes my goal is Use of capacitor plates movement to Calculate Acceleration in HSPICE
also acceleration type is transverse comb that you see on pic
my problem just write netlist for this section of circuit

Title: Re: variabe capacitor in hspice
Post by Geoffrey_Coram on May 13^th, 2015, 8:29am

I would probably write a Verilog-A model for the cap like:

module varcap(t, b, x);

and then instantiate it in the netlist as

xcap1 top bot xpos varcap ...

where "top" and "bot" are the electrical terminals, and "xpos" is a node that represents the position. You'll want to be sure to scale xpos (perhaps simply choose appropriate units) so that the tolerances are appropriate (eg, if the plates move in nanometers, then when you represent xpos as a voltage with vntol=1u, you completely lose all accuracy).

I've put xpos in the netlist, so I can connect other elements to it; you could also try to put all the mechanical components inside the Verilog-A module.

Title: Re: variabe capacitor in hspice
Post by vahid on May 13^th, 2015, 11:48am

thx for your answer

In order to simulate the transient response of the readout
circuit, a pair of time-varying sensor capacitors are required.
A simple varactor model is implemented in Verilog-A which
produces a voltage-controlled capacitor. This model has four
terminals, where two terminals are the capacitor terminals, and
the other are the voltage input terminals. The Verilog-A model
is built upon the following equation:
C = C0 + CV Vin (4)
Q = CVC (5)
IC = dQ/dt (6)
This model consists of a fixed capacitor C0, and a variable
capacitor CV . The model takes in a voltage Vin as an input and
provides a variable capacitor C. Note that VC is the voltage
across the capacitor C. In this design, C0 is assumed to be
100 fF, CV is 1 fF, and Vin can be any time-varying voltage
signal that controls the change in the output capacitance.

now i can't write this verilog-a model
and i dont know vin must be sin voltage or not?

Title: Re: variabe capacitor in hspice
Post by Geoffrey_Coram on May 15^th, 2015, 11:48am

Did you see the basic capacitor model here:
http://www.designers-guide.org/VerilogAMS/basic-models/capacitor/capacitor.va

Title: Re: variabe capacitor in hspice
Post by vahid on May 15^th, 2015, 2:39pm

yes but i dont know how define and write Vi and c=c0+c1vi equation in veriloge and use it in hspice :-[ :-[ :-[ :'( :'(

Title: Re: variabe capacitor in hspice
Post by Geoffrey_Coram on May 18^th, 2015, 7:14am

What is "veriloge" ?

Title: Re: variabe capacitor in hspice
Post by vahid on May 19^th, 2015, 1:09am

excuse me : verilog-a *

Title: Re: variabe capacitor in hspice
Post by Geoffrey_Coram on May 19^th, 2015, 11:09am

Step 1:
download the capacitor model; figure out the syntax to include it in your netlist, and run a simulation.

Title: Re: variabe capacitor in hspice
Post by vahid on Jun 13^th, 2015, 2:08pm

hii i write this verilog-a for variable capacitor and i test circuit in hspice but capacitor don't change While i expected capacitance change sinusoidal please help me

`include "constants.vams"
`include "disciplines.vams"

module vccap(Cp, Cn, Vp, Vn);

input Vp, Vn;
inout Cp, Cn;

electrical Cp, Cn, Vp, Vn;

real C;

parameter real C0 = 0;
parameter real CS = 2.5p;

analog begin

C = V(Vp,Vn);
I(Cp,Cn) <+ C * ddt(V(Cp,Cn));
end

endmodule

hspice test :

.hdl vccap.va
.options post=1

x1 1 2 3 4 vccap

vi 3 4 sin( 0 1 500k)

.tran 2n 500us

.PROBE tran cap(1,2) cap(1) cap(2)
.end

Title: Re: variabe capacitor in hspice
Post by Ken Kundert on Jun 14^th, 2015, 11:34am

Two things:

The equations for a linear capacitor is: q=Cv and i=dq/dv, thus i=d(Cv)/dt. In other words, your C should be inside the ddt operator, not outside.
I suspect the probe statement is not working as you hope. I recommend you just do an AC analysis and measure your capacitance that way.

-Ken

Title: Re: variabe capacitor in hspice
Post by vahid on Jun 14^th, 2015, 12:59pm

Ken Kundert wrote on Jun 14^th, 2015, 11:34am:

Two things:

The equations for a linear capacitor is: q=Cv and i=dq/dv, thus i=d(Cv)/dt. In other words, your C should be inside the ddt operator, not outside.
I suspect the probe statement is not working as you hope. I recommend you just do an AC analysis and measure your capacitance that way.

-Ken

thx Bro

Title: Re: variabe capacitor in hspice
Post by rockypn on Oct 29^th, 2015, 3:11pm

I am trying to use PWL to get the curve for CV anyone has been successful in doing it ?