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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Override parameters in Verilog-A subcircuit by Hspice for Monte Carlo simulation https://designers-guide.org/forum/YaBB.pl?num=1431985102 Message started by Joe Shmoe on May 18th, 2015, 2:38pm |
Title: Override parameters in Verilog-A subcircuit by Hspice for Monte Carlo simulation Post by Joe Shmoe on May 18th, 2015, 2:38pm Hi friends, I have a question. I have a sub-circuit defined by Verilog-A. Lets say: `include "disciplines.vams" module test05(na, nb); inout na, nb; electrical na, nb; parameter R2 = 1; analog begin I(na, nb) <+ V(na, nb)/R2; end endmodule Now I invoke this sub-circuit in Hspice. ... X1 1 0 test05 ... I would like to override the parameter R2 using an Hspice command. .param R2 = myvalue .options PARHIER = Global I tried this approach. but the value R2 in the subcircuit wasn't overridden. The ultimate goal is; to be able to run a Monte-Carlo simulation of the sub-circuit in Hspice. Any idea how to this? Thanks in advance, JS |
Title: Re: Override parameters in Verilog-A subcircuit by Hspice for Monte Carlo simulation Post by Geoffrey_Coram on May 18th, 2015, 6:50pm When you instantiate the Verilog-A in the HSpice netlist, shouldn't you specify the parameter there? ... X1 1 0 test05 R2=r2par ... .param r2par = myvalue I don't know what .option PARHIER = Global is supposed to do; I've never used it. |
Title: Re: Override parameters in Verilog-A subcircuit by Hspice for Monte Carlo simulation Post by Joe Shmoe on May 19th, 2015, 8:59am Hi Geoffrey, I usually have the parameter defined in the Verilog-A file as Parameter real R2 = value; so I usually just use X1 1 0 test05; without the parameter instantiation. If I instantiate the parameter R2 in the HSPICE netlist X1 1 0 test05 R2=value; the Verilog-A file does not take this value. I have attached the .sp and .va file that I run. The .option PARHIER = <Global|Local> is a command to to tell the system either to take the globally defined parameters (instantiation) or the locally defined parameters (.va file) in case there are overlaps of the parameter names... .sp file: *Title: test05 * test circuit for parameter scoping & passing .hdl test05.va * Circuit definition .PARAM r2par = 2 *.option PARHIER = Global X1 1 0 test05 R2=r2par V1 1 0 SIN(0 2 0.5 0) * Analysis .TRAN 0.1 2 .option post .end .va file: // test circuit for parameter scoping & passing `include "disciplines.vams" module test05(na, nb); inout na, nb; electrical na, nb; //parameter R2 = 2; analog begin I(na, nb) <+ V(na, nb)/R2; end endmodule |
Title: Re: Override parameters in Verilog-A subcircuit by Hspice for Monte Carlo simulation Post by Geoffrey_Coram on May 19th, 2015, 11:06am Hi, Joe - When you comment out the parameter declaration: Quote:
then I would expect the Verilog-A module would not compile, because it doesn't have a declaration of R2: Quote:
Perhaps your simulator was using the compiled object from before you commented out the declaration? When you do Code:
the value '2' is the default value. I think of Verilog-A working more like a built-in device rather than a subckt; a built-in diode has a parameter IS with a default of 1e-14, and you can't "undeclare" IS in the model and expect Code:
to have an effect. |
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