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Design Languages >> Verilog-AMS >> Comparator with Hysteresis without hidden states
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Message started by clidre on May 20^th, 2015, 6:14am

Title: Comparator with Hysteresis without hidden states
Post by clidre on May 20^th, 2015, 6:14am

Hello,
I wrote a code in VerilogA that models a fully-differential comparator with hysteresis, to be used in a pss.
The code works in transient simulations, but not in pss, because the variable vthaux has hidden states.
My code is the following:

Code:

`include "constants.vams"
`include "disciplines.vams"

module comp_hyst_FullyDiff_NH2(outp, outn, p, n);
output outp, outn;
electrical outp, outn;
input p,n;
electrical p,n;

parameter real input_offset=0;
parameter real hyst_offset=0.1;
parameter real trise=10p;
parameter real tfall=10p;
parameter real logic_high=1;

real voutp, voutn, vthaux;

analog begin

@(initial_step) begin

voutp=logic_high*((V(p)-V(n))>input_offset);
voutn=logic_high*((V(p)-V(n))<=input_offset);
vthaux=input_offset+hyst_offset*((V(p)-V(n))<=input_offset)-hyst_offset*((V(p)-V(n))>input_offset);

end

@(cross(V(p)-V(n)-vthaux));
begin
voutp=logic_high*((V(p)-V(n))>vthaux);
voutn=logic_high*((V(p)-V(n))<=vthaux);
vthaux=input_offset+hyst_offset*((V(p)-V(n))<=vthaux)-hyst_offset*((V(p)-V(n))>vthaux);
end

V(outp) <+ transition(voutp,trise,tfall);
V(outn) <+ transition(voutn,trise,tfall);

end
endmodule

I need that the variable vthaux (i.e. the threshold+hysteresis) is set to the right value at the initial step, so I cannot initialize it with a fixed value.
If I try a pss, I get the following error:

Code:

ERROR (SPCRTRF-15177): PSS analysis doesn't support behavioral module components with hidden states found in component 'comp_hyst_FullyDiff_NH2'. Skipped.

/misc/cadence/comp_hyst_FullyDiff_NH2/veriloga/veriloga.va, declared in line 22: Hidden state variable: vthaux

Do you know a way to remove the hidden states in vthaux? Thanks a lot!!!!

Title: Re: Comparator with Hysteresis without hidden states
Post by Peter Grove on Jun 15^th, 2015, 11:51am

I would avoid event driven blocks of code (cross/above/initial) and make it continious. The code below has no hidden states as none of the code is within an event driven block of code.

e.g. (Untested)

//Comparator model - continious time.
comp_out = (Vin > (Vref + (comp_out ? -hyst_neg:hyst_pos))) ? 1:0;
//Use above to create a timestep when it changes state.
@(above(comp_out-0.5,...) or above(0.5-comp_out,...));

For comp_out to go high vin > vref+hyst_pos, to then go neg vin < vref-hyst_neg.