The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Problem with wreal simulation - RNM Real Number Modeling
https://designers-guide.org/forum/YaBB.pl?num=1433344728

Message started by Zorro on Jun 3^rd, 2015, 8:18am

Title: Problem with wreal simulation - RNM Real Number Modeling
Post by Zorro on Jun 3^rd, 2015, 8:18am

Hi everybody,

here is a description of the problem I have.
I hope someone can help with a suggestion.
It is important to mention that am relatively new to RNM/wreal modeling (RNM=Real Number Modeling)

This is only for testing purposes but I am seeing some unexpected behavior.

I have two different versions of a stimuli block:
- one version uses electrical for inout pin vdd
- the other version uses wreal for inout pin vdd.

See picture 1.

Here is the code of both stimuli blocks and the table file:

------------------------------------------------------------------------
VERSION USING ELECTRICAL FOR INOUT PIN vdd

`timescale 1ns/1ps
`include "constants.vams"
`include "disciplines.vams"

module dut2_stim_vams (vcontrol ,vdd, vss, reset, ana_out1, ana_out2, ana_out3, ana_out4, dig_out1, dig_out2, dig_out3, dig_out4);

// Pin Directions
output vcontrol, reset, ana_out1, ana_out2, ana_out3, ana_out4, dig_out1, dig_out2, dig_out3, dig_out4;
inout vdd, vss;

// Pin Types
wreal ana_out1, ana_out2, ana_out3, ana_out4;
logic dig_out1, dig_out2, dig_out3, dig_out4;
logic reset;
electrical vcontrol ,vdd, vss;

// Variable Declarations
real vss_reg;
real simtime;
real vcontrol_reg;
real vdd_reg;
reg reset_reg;

// Core

initial begin
vss_reg = 0;
vcontrol_reg= 0;
vdd_reg= 0;
reset_reg = 1;
#250 reset_reg = 0;
end

always begin
#1
vcontrol_reg = $table_model($abstime,"vcontrol_stim.vat","1LL") ;
vdd_reg = $table_model($abstime,"vdd_stim.vat","1LL") ;
//vdd_reg = $table_model($abstime,"vcontrol_stim.vat","1LL") ;
end

//always begin
//#1000 $finish;
//end

analog begin
V(vdd) <+ vdd_reg;
V(vcontrol) <+ vcontrol_reg;
V(vss) <+ vss_reg;
end

assign reset = reset_reg;

endmodule

------------------------------------------------------------------------

VERSION USING WREAL FOR INOUT PIN vdd

`timescale 1ns/1ps
`include "constants.vams"
`include "disciplines.vams"

module dut2_stim_vams (vcontrol ,vdd, vss, reset, ana_out1, ana_out2, ana_out3, ana_out4, dig_out1, dig_out2, dig_out3, dig_out4);

// Pin Directions
output vcontrol, reset, ana_out1, ana_out2, ana_out3, ana_out4, dig_out1, dig_out2, dig_out3, dig_out4;
inout vdd, vss;

// Pin Types
wreal ana_out1, ana_out2, ana_out3, ana_out4;
logic dig_out1, dig_out2, dig_out3, dig_out4;
logic reset;
//electrical vcontrol ,vdd, vss;
wreal vcontrol ,vdd, vss;

// Variable Declarations
real vss_reg;
real simtime;
real vcontrol_reg;
real vdd_reg;
reg reset_reg;

// Core

initial begin
vss_reg = 0;
vcontrol_reg= 0;
vdd_reg= 0;
reset_reg = 1;
#250 reset_reg = 0;
end

always begin
#1
vcontrol_reg = $table_model($abstime,"vcontrol_stim.vat","1LL") ;
vdd_reg = $table_model($abstime,"vdd_stim.vat","1LL") ;
//vdd_reg = $table_model($abstime,"vcontrol_stim.vat","1LL") ;
end

//always begin
//#1000 $finish;
//end

// analog begin
// V(vdd) <+ vdd_reg;
// V(vcontrol) <+ vcontrol_reg;
// V(vss) <+ vss_reg;
// end

assign vdd = vdd_reg;
assign vcontrol = vcontrol_reg;
assign vss = vss_reg;

assign reset = reset_reg;

endmodule

------------------------------------------------------------------------

vdd_stim.vat

# time voltage
0 2.5
1u 2.4
2u 2.1
3u 2.0
4u 2.5
5u 2.0

------------------------------------------------------------------------

If a simulate the stimuli blocks alone (without connecting them to any other block) I get the expected behaviors. See picture 2.

Now if I connect a DUT (simple resistor voltage dividers which divide the input voltage by 2 and by 4) the electrical signal behaves correctly (as before) but the wreal signal behaves very strange, its value decreases. See pictures 3, 4, 5 and 6 below.

Any idea what could be causing this wrong behavior in the wreal vdd signal?

Title: Re: Problem with wreal simulation - RNM Real Number Modeling
Post by Zorro on Jun 3^rd, 2015, 8:20am

Picture 2

Title: Re: Problem with wreal simulation - RNM Real Number Modeling
Post by Zorro on Jun 3^rd, 2015, 8:20am

Picture 3

Title: Re: Problem with wreal simulation - RNM Real Number Modeling
Post by Zorro on Jun 3^rd, 2015, 8:20am

Picture 4

Title: Re: Problem with wreal simulation - RNM Real Number Modeling
Post by Zorro on Jun 3^rd, 2015, 8:21am

Picture 5

Title: Re: Problem with wreal simulation - RNM Real Number Modeling
Post by Zorro on Jun 3^rd, 2015, 8:21am

Picture 6

Title: Re: Problem with wreal simulation - RNM Real Number Modeling
Post by boe on Jun 3^rd, 2015, 10:04am

Zorro,
a resistor needs an "electrical", if you connect a "wreal" to it, a connect module (CM) is automatically inserted, which translates between "wreal" and "electrical".
A CM for translating from wreal to electrical typically uses a staircase mechanism and has an output impedance.
- B O E
PS: for convergence reasons, you should use a transition filter for an electrical pwl signal.

Title: Re: Problem with wreal simulation - RNM Real Number Modeling
Post by Zorro on Jun 4^th, 2015, 2:36am

Hi boe,

thanks for your reply. Below my comments and maybe you can add an extra comment to them.

1.
That means to compare the wreal model against the schematic (in the same testbench) the best is to use electrical pins for the analog stimuli signal rather than using wreal pins for the analog stimuli signal.
Doing so we avoid the insertion of ConnectModules for the connection wreal-->spectre(I mean the resistor inside the DUT) and we don't have the effects of the CM's output resistance.

2.
If we do as stated in 1., .... what about the ConnectModule for the connection electrical-->wreal ??? the CM's output resistance could also play a role here, or????

3.
Your PS. indicates the use of electrical pins for the analog stimuli signal rather than using wreal pins for the analog stimuli signal.
In this case there was no convergence problem using the electrical pin, but for complex DUTs (or in general) you recommend to do this:

V(vdd) <+ transition(vdd_reg, td, tf, tf);

correct?

Thank you for your advices.

Title: Re: Problem with wreal simulation - RNM Real Number Modeling
Post by boe on Jun 4^th, 2015, 8:22am

Zorro wrote on Jun 4^th, 2015, 2:36am:

1.
That means to compare the wreal model against the schematic (in the same testbench) the best is to use electrical pins for the analog stimuli signal rather than using wreal pins for the analog stimuli signal.
Doing so we avoid the insertion of ConnectModules for the connection wreal-->spectre(I mean the resistor inside the DUT) and we don't have the effects of the CM's output resistance.

Usually, yes.

Quote:

2.
If we do as stated in 1., .... what about the ConnectModule for the connection electrical-->wreal ??? the CM's output resistance could also play a role here, or????

No, because wreal only represents voltage, there is no output resistance. (NB: It is also time discrete.)

Quote:

3.
Your PS. indicates the use of electrical pins for the analog stimuli signal rather than using wreal pins for the analog stimuli signal.
In this case there was no convergence problem using the electrical pin, but for complex DUTs (or in general) you recommend to do this:

V(vdd) <+ transition(vdd_reg, td, tf, tf);

correct?

Yes.
- B O E

Title: Re: Problem with wreal simulation - RNM Real Number Modeling
Post by Zorro on Jun 5^th, 2015, 2:21am

thank you boe, it is clear to me now what is the best way to proceed.

I wanted to do a check, so I did this:

For this example the DUT internal resitance is:

Rdut = (1k+1k) // (3k+1k) = 2k // 4k = 1.333333k

From the pictures I can see that I get 2.15348V (vout) instead of the expected 2.5V (vin) at time 4us.

so:

vin * Rdut / (Rcm + Rdut) = vout

Rcm = Rdut * (vin - vout) / vout = 1.333333k * (2.5 - 2.15348) / 2.15348 ~ 214.5488 ohms

from the connect rules that I am using I found this:

connect R2E_2 #(.vsup(`Vsup), .vdelta(`Vdelta), .tr(`Tr_delta), .tf(`Tr_delta), .rout(`Rlo));

`define Vsup 1.8
`define Vdelta `Vsup/64
`define Tr 0.2n
`define Tr_delta `Tr/20
`define Rlo 200
...

which approximately matches the calculation that I did for Rlo.