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Design >> High-Power Design >> LV devices isolation in TSMC 0.18 high voltage BCD Gen2 process
https://designers-guide.org/forum/YaBB.pl?num=1434531720

Message started by xlowen on Jun 17^th, 2015, 2:02am

Title: LV devices isolation in TSMC 0.18 high voltage BCD Gen2 process
Post by xlowen on Jun 17^th, 2015, 2:02am

Hi Guys,

I am using TSMC 0.18 BCD process to design a HV ADC. the PDK I got from TSMC only gives example on how to put two 1.8V NMOS devices into one isolation ring. When I put 1.8V pmos & nmos into one isolation ring like I showed in the attached slides, however, the LVS reports an error (diode called nwdio_iso is missing in the schematic). Can anybody give some feedback on this issues?

The reason I want to share isolation ring between LV nmos & pmos is I want to isolate a LV folded cascode ampifier for noise consideration.

Thanks!

Title: Re: LV devices isolation in TSMC 0.18 high voltage BCD Gen2 process
Post by boe on Jun 18^th, 2015, 9:01am

Xlowen,
does your LVS rule file extract and compare parasitic diodes?
- B O E

Title: Re: LV devices isolation in TSMC 0.18 high voltage BCD Gen2 process
Post by xlowen on Jun 18^th, 2015, 12:18pm

Hi Boe,

Thanks for your reply. Yes, I enabled the option to extract parasitic diodes.
I guess the 1.8V PMOS can not be generated based on HV NWell/NBL. Otherwise, the LVS should not give that error: "parasitic diode nwdio_iso
(which is between 1.8V NW and PSUB) is missing."

Thanks
xlowen

Title: Re: LV devices isolation in TSMC 0.18 high voltage BCD Gen2 process
Post by boe on Jun 19^th, 2015, 4:26am

xlowen,
then you need the parasitic diodes (e.g. between the wells) in the schematic as well.
- B O E

Title: Re: LV devices isolation in TSMC 0.18 high voltage BCD Gen2 process
Post by boe on Jun 19^th, 2015, 7:07am

xlowen wrote on Jun 18^th, 2015, 12:18pm:

I had a closer look, and I am not sure your construct is the intended use case. It seems that in the schematic the parasitic diode is missing.
- B O E

Title: Re: LV devices isolation in TSMC 0.18 high voltage BCD Gen2 process
Post by xlowen on Jun 20^th, 2015, 2:56am

Hi Boe,

I am just confused by the PDK I got from TSMC. In one document, the LV isolation is like fig1, for this case, two parasitic diodes(PW/NBL & NBL/PSUB) are added in the schematic below by myself, the other shows LV isolation like fig2, in which three diodes(NW/PW & PW/NBL & NBL/PSUB) are required.
from LVS results I got, it seems the latter one is correct.

xlowen