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Design >> Mixed-Signal Design >> Verilog HDL simulation with ams simulator
https://designers-guide.org/forum/YaBB.pl?num=1436782927

Message started by medya on Jul 13^th, 2015, 3:22am

Title: Verilog HDL simulation with ams simulator
Post by medya on Jul 13^th, 2015, 3:22am

Hi all,

I wonder whether is it possible to simulate a Verilog HDL code (digital block) without any manipulation with ams simulator? I did a simple simulation as you see in the attached pictures, however after simulation it seems that the outputs are something not well defined! Do I need to define any discipline or add extra lines inside the block code to make the simulation possible? Actually I don't want to make big changes inside my original HDL code:)!
the Verilog hdl code inside the digital block is:

module testofhdl ( co, sum, a, b, ci, clk );
//Input declaration
input a, b, ci,clk;
//Ouput declaration
output co, sum;
//Port Data types
reg co, sum;
always @ (posedge clk)
assign {co, sum}= a+b+ci;
endmodule

Regards,

Medya

Title: Re: Verilog HDL simulation with ams simulator
Post by Ken Kundert on Jul 13^th, 2015, 12:58pm

I believe your Verilog code is fine (does not need to be changed). Instead, I suspect your connect modules are not working correctly. If you set up your outputs correctly and you asked for the hdl variables to be saved, you should be able to view the values of the variables in your hdl module. Check to assure that your clock is coming in as expected. It may be that the supply voltages are not set on your connect modules, which means that the connect module threshold is not being crossed, so your clock edges are not registering properly.

-Ken