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Design >> Analog Design >> PLL Design
https://designers-guide.org/forum/YaBB.pl?num=1437364711

Message started by Sushanthhegde3 on Jul 19^th, 2015, 8:58pm

Title: PLL Design
Post by Sushanthhegde3 on Jul 19^th, 2015, 8:58pm

What is coarse and fine integration in PLL Design?

Title: Re: PLL Design
Post by loose-electron on Jul 20^th, 2015, 10:53pm

probably two different current setting for the charge pump.

Fast acquire PLL's sometime use a structure where the charge pump goes into high current mode when starting lock up, and then drops to lower current as the loop gets closer to phase lock.

Allows for a faster frequency acquisition and phase pull in process.

Title: Re: PLL Design
Post by Sushanthhegde3 on Jul 20^th, 2015, 11:07pm

Hello,

Thank you for the reply.

If my loop filter has second order transfer function,then how can I know when is coarse integration and fine integration is taking place?
Could you please point me to the architecture you are referring to?

Thank you.

Title: Re: PLL Design
Post by loose-electron on Jul 21^st, 2015, 6:55pm

I have used the described architecture for timing clock acquisition. Is it in a paper someplace? I have no idea.

What I did (it was a disk drive read channel) was go high current for the first 10 cycles of the header preamble and then flip to lower current. This got you closer on frequency very quickly.

Title: Re: PLL Design
Post by rfmagic on Jul 23^rd, 2015, 11:25am

In the same direction as Loose-Electron has pointed out, it may also be the case where the loop BW has 2 modes i.e. high BW mode for fast acquisition and low BW mode for normal operation for optimal PN

Title: Re: PLL Design
Post by Sushanthhegde3 on Jul 24^th, 2015, 3:05am

Thank you for the explaination. I have another query.The bang bang phase detectors used in ADPLL can measure the phase of early or late signals.If the reference is leading then early will be at logic 1 and if the feedback is leading then the late signal will be at logic 1.In some literatures I came to know that the BBPD can measure the frequency difference too.Could you plz help me to understand?

Thanks in Advance :)

Title: Re: PLL Design
Post by loose-electron on Jul 27^th, 2015, 10:31am

Sushanthhegde3 wrote on Jul 24^th, 2015, 3:05am:

THis is the difference between a

Phase Detector (PD)
and a
Phase-Frequency Detector (PFD)

A PFD will tell the PLL to go up or down until the frequency is the same and then just adjust for phase.

A PD will give a mixture of up-down information depending on the instant phase relationship of the two signals.

I am sure there is some information out there on this. Look for timing diagrams of the PFD and PD to see a comparison.