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Design Languages >> Verilog-AMS >> Modelling an incremental current source
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Message started by Rosh on Aug 19^th, 2015, 8:03pm

Title: Modelling an incremental current source
Post by Rosh on Aug 19^th, 2015, 8:03pm

I am trying to build a non-ideal voltage source with a drooping characteristic for increasing current that is drawn from the source.

So far my circuit consists of a voltage source in series with a resistance (which is the internal resistance) supplying a fixed capacitor load.

I now want to add a current source which keeps sinking increasing amount of currents from voltage source.

Is there any way to do this?

I want to accomplish this :
Code:

I(n1,n)<+ dc+ 0.1 ;

i.e the current source should draw 0.1A more current for each simulation time.

How do I accomplish this? The for loop doesn't work

Title: Re: Modelling an incremental current source
Post by boe on Aug 21^st, 2015, 2:15am

Rosh,

Quote:

i.e the current source should draw 0.1A more current for each simulation time.

In transient simulation, the time steps may be unequal, so you should use something like I(tsim) = Idc + Gain * tsim.
- B O E

Title: Re: Modelling an incremental current source
Post by Rosh on Aug 23^rd, 2015, 11:56pm

Thank you B O E. It works now :) 8-)