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https://designers-guide.org/forum/YaBB.pl Simulators >> Circuit Simulators >> Phase locked loop dead zone simulation using Spectre and Virtuoso https://designers-guide.org/forum/YaBB.pl?num=1441338423 Message started by Rosh on Sep 3rd, 2015, 8:47pm |
Title: Phase locked loop dead zone simulation using Spectre and Virtuoso Post by Rosh on Sep 3rd, 2015, 8:47pm Hi I'm trying to simulate the dead-zone present in the phase frequency detector of a PLL. This is the structure of the PFD I am using. I have added a delay in the reset path after the NAND gate. Here are the specs for pulse generators A and B. Period : 2us Width: 1us Rise/Fall : 50ns UP is QA If there is a delay of 1us between A and B, QA(UP) is able to capture the phase difference (after I added the delay block of 1us in the reset path) Waveform: However, for a smaller delay , say 500ns, and a delay block of 500ns in the reset path, I get this waveform. A 500ns phase difference captured on QA(UP), but I also get another pulse for 500 after that. The same goes for any phase delay less than 1us. Why do I get this additional pulse on QA(UP)? |
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