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Design Languages >> VHDL-AMS >> Generic port width
https://designers-guide.org/forum/YaBB.pl?num=1441792159

Message started by Sammekevremde on Sep 9^th, 2015, 2:49am

Title: Generic port width
Post by Sammekevremde on Sep 9^th, 2015, 2:49am

Hi i'm using cadence virtuoso and i'm trying to use a generic to determine the port width in a vhdl entity.

entity Voter is
generic ( width : integer := 8 );
Port ( input1 : in STD_LOGIC_VECTOR (width-1 downto 0);
input2 : in STD_LOGIC_VECTOR (width-1 downto 0);
input3 : in STD_LOGIC_VECTOR (width-1 downto 0);
output : out STD_LOGIC_VECTOR (width-1 downto 0));
end Voter;

when i compile this it gives me the warning.

*WARNING* (DB-270000): dbCreateNet: Input name(or member) : input<width-1:0> has improper bus syntax
*Error* dbCreateTerm: argument #1 should be a database object (type template="dgtxg") - nil
Error failed to create shadow database for (work voter entity).

i've tried to put brackets around the (width-1) which doens't work either.

Title: Re: Generic port width
Post by boe on Sep 10^th, 2015, 5:08am

Sammekevremde,
AFAIK Cadence Virtuoso (Schematic/Symbol editor) does not support this.
- B O E

Title: Re: Generic port width
Post by Sammekevremde on Sep 10^th, 2015, 11:49am

Thank you Boe.

To bad it isn't supported, would be really nice to be able to use a component multiple times with different parameters.