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Design >> Mixed-Signal Design >> values of R & C in active-RC filter in sigma-delta ADC
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Message started by AZADBAKHT on Sep 16^th, 2015, 4:11am

Title: values of R & C in active-RC filter in sigma-delta ADC
Post by AZADBAKHT on Sep 16^th, 2015, 4:11am

hi all

i want to design a sigma-delat ADC with 16bit resolution as 2'order loop.
i simulated it in matlab software as system level, now i want design filters loop as active-RC, but i don't know how to choice R & C values!!
can anyone help me to resolve this problem?

best of regards,
azadbakht

Title: Re: values of R & C in active-RC filter in sigma-delta ADC
Post by cheap_salary on Sep 16^th, 2015, 4:53am

See Table 9.6 at page-322 of the following book.
http://www.amazon.com/Understanding-Delta-Sigma-Converters-Richard-Schreier/dp/0471465852/ref=sr_1_1?ie=UTF8&qid=1319934940&sr=8-1

Title: Re: values of R & C in active-RC filter in sigma-delta ADC
Post by AZADBAKHT on Sep 17^th, 2015, 5:12am

tnx a lot sir cheap_salary

Title: Re: values of R & C in active-RC filter in sigma-delta ADC
Post by saralandry on Nov 30^th, 2015, 6:50pm

Hi,

To determine the resealable values for R and C in an active RC-integrator used in a CT-DSM, you have to consider input thermal noise. feedback DAC as well as resistor have constrictions on overall input noise of the integrator. Having had noise power, you can determine the value of the resistor. And then C. You have to set the integrator pole at 1/RC. It is fairly easy.

Title: Re: values of R & C in active-RC filter in sigma-delta ADC
Post by deltasigmaADC on Feb 1^st, 2016, 4:05am

The scaling factor in each integrator of a CTDSM is Fs(sampling frequency). So typically 1/RC = Fs. Now you need to have feedback coefficients for each paths. In your case since second order two paths (1/s and 1/s^2). And direct path if compensated for excess loop delay.

Now these coefficients can be added to the 1/RC or at the DAC itself. That is a choice that you have to make. Typically for the first integrator R is fixed for thermal noise spec. For other integrators you can choose a R and C such that they are not too large in layout and not too small to get affected by parasitics. Also take into consideration area.

One more thing you have to take into account is the swing at the output of each integrator. Best design practice is to scale the swing to the max swing an opamp can support so that your passives won't get too big. Use node scaling for that.
These scaling factor will also come in the RC time constant of integrator.

You can watch video lectures of Dr Shanti Pavan of IIT Madras for a detailed understanding.

http://nptel.ac.in/courses/117106034/
http://www.ee.iitm.ac.in/vlsi/