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Design Languages >> Verilog-AMS >> PLL loop filter issue for veriloga model simulation.
https://designers-guide.org/forum/YaBB.pl?num=1442510386

Message started by Homer on Sep 17^th, 2015, 10:19am

Title: PLL loop filter issue for veriloga model simulation.
Post by Homer on Sep 17^th, 2015, 10:19am

Hi,

I'm trying to implement a veriloga model for my pll design to predict jitter. I copied the block models from Ken's paper and merged them into one PLL loop schematic. For the loop filter I just use ideal devices with reasonable resistance and capacitance value. Please check the schematic drawing.

But the simulation is weird. It seems the simulator removed these LPF devices. The vcoin voltage is Mega Volt once chpp output current. And I can't find the node between resistor and capacitor in the simulation result.

Title: Re: PLL loop filter issue for veriloga model simulation.
Post by Homer on Sep 17^th, 2015, 10:25am

Add the simulation result

Title: Re: PLL loop filter issue for veriloga model simulation.
Post by Homer on Sep 17^th, 2015, 10:41am

Sorry. It's not simulator and model issue.

I put symbol before spectre in the view list. And the netlistor didn't create these device in the netlist.