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https://designers-guide.org/forum/YaBB.pl Simulators >> RF Simulators >> Question about simulating noise of switched capacitor S/H https://designers-guide.org/forum/YaBB.pl?num=1442683261 Message started by neoflash on Sep 19th, 2015, 10:21am |
Title: Question about simulating noise of switched capacitor S/H Post by neoflash on Sep 19th, 2015, 10:21am Hi, I have a question about simulating the noise of a S/H circuit. The method I am using right now is to simulate noise in sample and hold phase separately. First, I put it in sample mode and simulate the noise over the sampling capacitor (CS) and hold capacitor (CH). I used HSPICE .NOISE and integrated over entire frequency band. The result seems to match KT/C closely. However, later I added a switch as noted in the diagram (represented by the red resistor Rp). If I use the noise voltage across capacitor + Rp, the noise is much higher. Rp contributes a lot of noise at higher frequency. And I think I should use the noise voltage across the capacitor Cs only since it is the charge noise that we care. Shall I include Rp in sample phase noise integration? Thanks! |
Title: Re: Question about simulating noise of switched capacitor S/H Post by Frank Wiedmann on Sep 21st, 2015, 12:49am For detailed information on how to simulate this kind of circuit, take a look at http://www.designers-guide.org/Analysis/sc-filters.pdf, http://go.mentor.com/4gfmm and http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6218338. Please note that the relatively new fullspectrum option (see http://www.designers-guide.org/Forum/YaBB.pl?num=1413365305/4#4) is not yet mentioned in these presentations. |
Title: Re: Question about simulating noise of switched capacitor S/H Post by neoflash on Sep 21st, 2015, 8:23am Thanks. I happen to watched this video yesterday. It is helpful. I think from Equipartition theorem point of view, Rp should not matter for phase 1's total noise charge. Frank Wiedmann wrote on Sep 21st, 2015, 12:49am:
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