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Design Languages >> Verilog-AMS >> AMBA architecture
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Message started by sai ganesh on Oct 13^th, 2015, 4:20am

Title: AMBA architecture
Post by sai ganesh on Oct 13^th, 2015, 4:20am

In AHB protocol i have address and data . When i am testing that the address should get in one clock and the data should get after one clock period of address . Can any one tell me about this . please immediately.

if possible send me a test bench code for AHB protocol.for both master and slave.