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Design Languages >> Verilog-AMS >> Veriog ams for voltage controlled oscillator: output frequency= input*gain
https://designers-guide.org/forum/YaBB.pl?num=1444792426

Message started by Rosh on Oct 13^th, 2015, 8:13pm

Title: Veriog ams for voltage controlled oscillator: output frequency= input*gain
Post by Rosh on Oct 13^th, 2015, 8:13pm

Hi

I want to build a verilog ams based clock pulse generator which takes in an input voltage and then gives me a frequency which is a particular gain*input voltage

How do I implement this particular frequency voltage relation?