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Modeling >> Behavioral Models >> modeling delays/ generate pulse
https://designers-guide.org/forum/YaBB.pl?num=1446119628

Message started by analogrf on Oct 29^th, 2015, 4:53am

Title: modeling delays/ generate pulse
Post by analogrf on Oct 29^th, 2015, 4:53am

My veriloga behavioural produces a short pulse when a voltage vA
crosses the a threshold vThresh. I am using the analog construct for this (with or without @cross). Unfortunately I cannot model that
pulse delay properly. The output trigOut is asserted "high" but it does
not toggle down, after the short delay.

Am I modelling the delay correctly?

-------------

analog begin
//@(cross(V(vA) - V(vThresh),+1,0.01n))
if ( V(vA) - V(vThresh) >= 0.0 ) begin
$strobe("Hi");
trg=1.5;
end
V(trigOut) <+ transition(trg,10n,10n,10n);
trg=0.0;
V(trgOut) <+ transition(trg,1u,10n,10n);
//V(trgOut) <+ absdelay(trg,1u)
end

------------------
Thanks and looking forward,
A.

Title: Re: modeling delays/ generate pulse
Post by boe on Oct 29^th, 2015, 10:27am

Analogrf,
the transition filter runs in parallel to your assignments to trg.
you need to create the pulse you want in trg, using the transition filter only to smooth out the transitions.
- B O E

Title: Re: modeling delays/ generate pulse
Post by Ken Kundert on Oct 29^th, 2015, 11:01am

You should try something like this:

Code:

analog begin
@(cross(V(vA) - V(vThresh),+1)) begin
t_reset = $abstime + 10u;
trg=1.5;
end
@(timer(t_reset))
trg = 0;
V(trigOut) <+ transition(trg,0,10n);
end

This follows B O E's suggestion of creating the pulse you want in trg, and then using transition only to smooth it.

-Ken

Title: Re: modeling delays/ generate pulse
Post by analogrf on Oct 30^th, 2015, 7:00am

Thanks BOE and Ken. The code snippets were helpful, and made
me skim through the entire manua (Cadence version)l. Some rules for Concurrency, race conditions etc., were helpful. Any other documents that you suggest might be helpful too.

Title: Re: modeling delays/ generate pulse
Post by analogrf on Oct 30^th, 2015, 7:05am

One more query: Would it be valid to read a port and write it, in the same construct, e.g. a simple example would be:

analog begin
if (V(level) >=1.2) begin
$strobe("detected");
trg=1;
end
V(level) <+ transition(trg,0,10n);
end

-AR

Title: Re: modeling delays/ generate pulse
Post by boe on Oct 30^th, 2015, 10:07am

Analogrf,
what is that supposed to achieve? But yes, syntactically that's OK.
- B O E

Title: Re: modeling delays/ generate pulse
Post by analogrf on Nov 2^nd, 2015, 9:19am

Ok, my mistake. V(level) would never change.

In the previous example code given by Ken, I just wanted to add
one more functionality: i.e. reset the voltage vA for a brief interval of ns to a given voltage 'reset', once the threshold is crossed. 'reset' voltage is also provided by another inout port. In the absence of 'trig' vA should retain its original voltage.

To do this I thought about a simple ternary operator at the end of analog construct (below the @timer) as:

V(vA) <+ (trig)? reset : V(vA);

The above code is however rather odd, as it retains the old value, in the else case. The simulator however does not like it.

In the else-condition I want to do *nothing*, such that vA retains its original value, but could not find an undefined state which I could assign to the else case of the ternary operator.

There is probably some straightforward way to achieve this, but no luck so far.

-A.

Title: Re: modeling delays/ generate pulse
Post by Ken Kundert on Nov 2^nd, 2015, 9:53am

Your intuition seems way out of whack when it comes to Verilog-A. The contribution statement is really an equation (with the constraint that the left-hand side must be a signal) rather than an assignment.

In an assignment it makes perfect sense to say:

Code:

i = i;

In doing so, you don't actually change i. But as an equation it makes no sense. It contains no information. If you try to use:

Code:

V(vA) <+ V(vA);

in the simulator you will end up with a singular Jacobian. Essentually you have more unknowns than you have equations because one of the equations you gave was defective.

Perhaps if you took a look at Introduction to Verilog-A it would help.

Of course there is another issue with what you propose. You are driving V(vA) with a voltage source, meaning that its voltage could not be affected by the outside circuit. Perhaps what you want is to add a switch. Something like

Code:

if (trg > 0.75)
V(vA) <+ reset;
else
I(vA) <+ 0;

. But doing so seems like a very bad idea, as you are driving your input. You are very likely to build either an oscillator or an unresetable latch.

-Ken