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Design >> High-Speed I/O Design >> Checking for stability in a bang bang CDR
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Message started by Venky_analog on Nov 18^th, 2015, 11:46pm

Title: Checking for stability in a bang bang CDR
Post by Venky_analog on Nov 18^th, 2015, 11:46pm

Hello,

I am working on a bang-bang CDR. There is one thing that's bothering me a lot. How to check for stability of this CDR, as bang-bang PD is a non-linear element. I read this paper by Ken :)

"Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits"

I can understand the approximate expressions for Jitter Transfer Function, Jitter Tolerance etc. but I couldn't find out how to actually check for the stability of this CDR loop. Since this is a non-linear element, how would we define the damping factor or closed loop poles or phase margin in such systems?

I will be really happy if someone could tell me how to check for stability (or design for good phase margin) in a bang-bang CDR. Thanks in advance.

Title: Re: Checking for stability in a bang bang CDR
Post by raja.cedt on Nov 19^th, 2015, 12:23am

Hello--
Yes Bang-bang phase detector is non-linear hence, linearized model can be used when phase error close to 0 (that's where it locks any way).This has been derived based on distribution of input jitter.

Phase detector gain---For random jitter---0.399/Sigma.
---For uniform distribution---0.288/Sigma.

Get the rest of the Z-domain transfer functions like loop filter,Phase interpolator(or VCO), loop delay and plot the transfer functions. You will see loop bandwidth and closed loop peaking.

refer the following pap---
A Digital Clock and Data Recovery Architecture
for Multi-Gigabit/s Binary Links

Thanks,
Raj.

Title: Re: Checking for stability in a bang bang CDR
Post by Venky_analog on Nov 19^th, 2015, 9:26am

Thank you very much for replying.

There is one thing that's bothering me.

Bang-bang PD is linear over a very small difference in phase. How can we check stability of the complete system by assuming the linearized model. Even a small signal would make it move to non-linear region and I don't know what will happen to the stability of the loop when that happens.

By the way, I am implementing an analog loop filter and not digital.

Thanks in advance.

Title: Re: Checking for stability in a bang bang CDR
Post by raja.cedt on Nov 20^th, 2015, 3:30am

Hello--
Yes that's true, it is hard non-linear circuit. That's why full transistor simulation and behavioural model sim gives full picture of stability at the cost of Sim time. I did few years back the same and results not close but good enough for any traditional CDR, but some how I saw better high frequency jitter tolerance compared to small signal model. Fortunately when the bandwidth is very less compared to data rate rate(~1/5000-2000) stability always looks good due to lower update rate.

Thanks,
Raj.

Title: Re: Checking for stability in a bang bang CDR
Post by BackerShu on Jan 17^th, 2016, 2:08am

If you are really interested, pleases read Jaeha Kim PhD thesis, Starting from Page 143. He treated it as bang-bang controlled loop, which is common in control theory. It is a nice reading.