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Design Languages >> Verilog-AMS >> Need some help with this code
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Message started by wandola on Nov 19^th, 2015, 7:18pm

Title: Need some help with this code
Post by wandola on Nov 19^th, 2015, 7:18pm

I am trying to write some code for a digital circuit.

module Processor(count,residue,out)
input [7:0] count;
input [4:0] residue;
output [12:0] out;

wire [12:0] mem, tmp1,tmp2,tmp3;

reg [4:0] coeff = 5'b10110;

assign tmp1 = count*coeff;
assign tmp2 = tmp1 + residue;
if (tmp1>mem)
assign tmp3 = tmp2-mem;
else
assign tmp3 = tmp+coef - mem;

assign mem = tmp2;
assign out = tmp3;

endmodule

I am using cadence nc-verilog for the design. the error msg says
if(tmp3 > mem): illegal operand for constant expression

can anybody help with this? really confused... Or, how shall I manage this?

Title: Re: Need some help with this code
Post by Torq on Nov 23^rd, 2015, 5:41am

Hi, wandola!

It seems, you sould use a multiplexer instead of if/else construction:

assign tmp3 = (tmp1>mem) ? tmp2-mem : (tmp+coef - mem);