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Design Languages >> Verilog-AMS >> Wreal
https://designers-guide.org/forum/YaBB.pl?num=1448469793

Message started by Adam_N on Nov 25^th, 2015, 8:43am

Title: Wreal
Post by Adam_N on Nov 25^th, 2015, 8:43am

Hi,
I'm new here and in Verilog-AMS modelling with data type wreal.

I propose to simulate a VHDL file with a few Verilog-AMS models (ADC, DAC and a plant transfer function) in irun environment.

1. Can the function @(cross(V(clk)-vth, +1)) be solved by irun
simulator?
If not, is there any simpler way to model behavior of a 10b ADC
and DAC?
2. How looks like the Verilog_AMS model (with wreal data type) for a
second order transfer function, sampled by Fs, like this
H(s)=(s^2+ωz/Qz s +ωz^2)/(s^2+ωp/Qp s +ωp^2)

Thanks a lot in advance!

Cheers!
Adam_N

Title: Re: Wreal
Post by AMS_ei on Jul 30^th, 2016, 5:20am

Hi,

wreal is a mixed signal variable. It is discrete in time and continuous in value. Hence, it uses digital solver to avoid convergence issues.

As it is uses event solver, hence it cannot be used in analog block. You have to use adsdelta () function to sample from analog value and then assign it to the wreal variable.

Hope this helps.

Thank you.

Title: Re: Wreal
Post by Ken Kundert on Aug 2^nd, 2016, 4:56am

For an example wreal dac, take a look at http://www.designers-guide.org/Books/dg-vams/ch4/ch4-listing09.tgz

-Ken