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Design Languages >> Verilog-AMS >> the problem of AMS code for capacitor
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Message started by eeBismarck on Dec 12^th, 2015, 9:03am

Title: the problem of AMS code for capacitor
Post by eeBismarck on Dec 12^th, 2015, 9:03am

Hi Guys,

I am a beginner who is learning the verilogA by myself. Today I use the following code to model a capacitor

`include "constants.vams"
`include "disciplines.vams"

module sjw_cap(p, n);
parameter real C = 0; // capacitance
inout p,n;
electrical p,n;
analog
I(p,n) <+ ddt(C*V(p,n));
endmodule

when I run the transient simulation, and give the since wave as input. I find that the AC current is 0. Could you give me some clue ?

BR

Title: Re: the problem of AMS code for capacitor
Post by Geoffrey_Coram on Jan 5^th, 2016, 6:29am

Did you specify a non-zero value for C in the netlist? You could try setting the default to 1p to see if there's a problem passing the value from the instance line.