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Design >> RF Design >> Would it be possible to design a SoC with two antenna?
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Message started by TurboV on Dec 13^th, 2015, 8:16pm

Title: Would it be possible to design a SoC with two antenna?
Post by TurboV on Dec 13^th, 2015, 8:16pm

If you use an actual SoC such as the Qualcomm Snapdragon Processor for mobile communications would it be possible to have two cores both sharing a common IO (Cellular/WiFi/GPS/Bluetooth) integrated circuits but its own separate antenna ? Would the baseband processor and lna amplifier modulator oscillator be required to be located only at the top most layer (where inductors are found) of the die ? So would this mean it is not possible to have two cores with its own separate antenna if the one of the cores is located somewhere other then on the top most layer since the lna amplifiers oscillators baseband processor are located on the top layer ?

Title: Re: Would it be possible to design a SoC with two antenna?
Post by loose-electron on Dec 14^th, 2015, 10:05pm

Research the concept of "software defined radio" and see if that answers your question.

Title: Re: Would it be possible to design a SoC with two antenna?
Post by TurboV on Dec 14^th, 2015, 11:40pm

loose-electron wrote on Dec 14^th, 2015, 10:05pm:

Research the concept of "software defined radio" and see if that answers your question.

Hello loose-electon. Thank you for the response. I did take a look at the SDR resources online. However I thought I should explain the rational behind the question asked on this forum. What I would like to learn is not how to go about designing and implementing such a technology (using two antennas) but whether it could be done.

So having said the above would you help in understanding whether two separate antennas operating with different frequency ranges could work effectively ? Also if the technologies to support two antennas could exist would it be possible to implement two different baseband IC's for two separate transceivers located on different layers of the SoC die ? Or having two antennas using different frequency range could and be implemented by one common transceiver and baseband IC's ?

I hope that my understanding of the above RF technologies are not misunderstood.

Thank you for the comments

Title: Re: Would it be possible to design a SoC with two antenna?
Post by loose-electron on Dec 20^th, 2015, 10:31pm

On the same chip is possible - however having multiple transmitters alive at the same time will probably be a problem. As well, having the LNA and RF front ends running on the same chip as a digital baseband is often a problem due to noise coupling.

What is possible and what can be easily done are often two different things. Isolation problems are very problematic.

Title: Re: Would it be possible to design a SoC with two antenna?
Post by TurboV on Dec 27^th, 2015, 11:46pm

loose-electron wrote on Dec 20^th, 2015, 10:31pm:

Thank you again loose-electron. Could you answer one more question ? If it is possible without the potential for noise coupling could the two transceivers exist on the same layer and if only one transceiver is deployed could this single transceiver IC be located anywhere on the die or would it have to be located right on the top most layer of the die ?

Thanks

Title: Re: Would it be possible to design a SoC with two antenna?
Post by loose-electron on Dec 28^th, 2015, 4:03pm

You talk about layers in the IC as if they are a multi floor building.

Generally the base layers of an IC are where the transistors are defined and created.
Upper layers of the chip are used for metal interconnection.

Consequently any device will reside on all layers of the semiconductor.

Title: Re: Would it be possible to design a SoC with two antenna?
Post by TurboV on Dec 28^th, 2015, 9:05pm

loose-electron wrote on Dec 28^th, 2015, 4:03pm:

Thank you again loose-electron.

My understanding of how a die of an IC is implemented is with multiple layers with each layer stacked over the next. So using an example of the Qualcomm Snapdragon SoC 810/820 IC I assumed this 3D IC would have multiple active layers (with silicon gate transistors integrated circuits) all interconnected vertically to the layer above and below ?

Then would you be saying that that most IC's (such as the Snapdragon 810/820) have only a few main (base) active layers and the rest (upper and or lower) are for metal interconnections ? So the base layers are at the bottom of the die and the upper layers are for the metal interconnections ?

Assuming that I have understood your response properly then could it possible in practice to have two transceivers (baseband IC and front ends) located either on the same base layer or on two different base layers ?

Many thanks for the responses.

Title: Re: Would it be possible to design a SoC with two antenna?
Post by loose-electron on Dec 30^th, 2015, 7:05pm

stacked die are starting to happen on a lot of newer designs, however the need for this is generally in high density logic chip stacks that I am aware of.

Stacking a lot of RF front ends together is asking for problems in noise and cross coupling problems.

To directly answer your question --- In practice it is possible. However there will probably be many difficulties to work out.

Title: Re: Would it be possible to design a SoC with two antenna?
Post by TurboV on Dec 31^st, 2015, 12:01am

loose-electron wrote on Dec 30^th, 2015, 7:05pm:

Thank you again loose-electron. Thanks for the answer to the multi transceiver on die. As for stacked die do you mean that an IC such as the Qualcomm SoC 810/820 may have multi dies all in the same package ? So each die has 1-2 base layers and the rest are for like you said metal interconnections ? If this is true then having two transceivers (two front ends two separate antennas) not work on a separate dies but all enclosed in the same package ?

Thank you (Happy New Year)

Title: Re: Would it be possible to design a SoC with two antenna?
Post by loose-electron on Jan 10^th, 2016, 7:33pm

Qualcomm and other IC vendors have been doing a number of different strategies here including:

Single die in single package.

Multiple die side buy side in a single package

Stacked die, with a smaller die bonded down on top of another die.
(RF front end glued on top of a baseband chip and others)
This also allows "mixing of foundry processes" where the two die are different technology.

Stacked die with interconnect between the die (matched size with specialty connection methods)