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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Problem of transition delay used in DTC verilog-A model https://designers-guide.org/forum/YaBB.pl?num=1451362866 Message started by Hamlee on Dec 28th, 2015, 8:21pm |
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Title: Problem of transition delay used in DTC verilog-A model Post by Hamlee on Dec 28th, 2015, 8:21pm Dear all, I am modeling a digital to time converter(DTC) using verilog-a code, and I met a negative delay problem. The spectre simulator always terminated when the DELAY move from a larger delay(say DELAY=100ps) to a small delay(say DELAY=20ps). Adding a fixed delay before DELAY will solve the problem, but I do not expect this fixed delay in my circuit design. Is there any better way to solve my problem? Best regards, Code:
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Title: Re: Problem of transition delay used in DTC verilog-A model Post by Ken Kundert on Dec 28th, 2015, 10:28pm Spectre should not have any trouble with a decreasing delay. Perhaps you can show the results. -Ken |
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Title: Re: Problem of transition delay used in DTC verilog-A model Post by Hamlee on Dec 29th, 2015, 8:59pm Dear Kundert, Thanks for your reply and suggestion. In simulation, if I keep increasing the delay (say DELAY = 10ps, 20ps, 30ps ....), it seems no problem at all. But if I decrease the delay (say DELAY = 320ps, 3ps), the error shows up. I attached the error message from spectreverilog simulator. |
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Title: Re: Problem of transition delay used in DTC verilog-A model Post by Ken Kundert on Dec 30th, 2015, 10:54pm It seems like a good error message. Have you tried bounding the delay so that it does not go negative? -Ken |
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Title: Re: Problem of transition delay used in DTC verilog-A model Post by Hamlee on Jan 5th, 2016, 3:40am Dear Kundert, Thanks for your reminding. I finally realized my problem that I used an unbounded delay in transition statement. It will cause the delay go negative but the transition expression does not support the negative delay statement. I bounded the delay and it works! |
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Title: Re: Problem of transition delay used in DTC verilog-A model Post by Geoffrey_Coram on Jan 5th, 2016, 6:24am How are you getting a negative value for DELAY? Are some of the voltages dipping below zero (perhaps briefly due to capacitive coupling)? |
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Title: Re: Problem of transition delay used in DTC verilog-A model Post by Hamlee on Jan 5th, 2016, 7:00am Hi, There was no negative DELAY generated. The negative delay error in spectre shown in figure is owing to the unbounded DELAY in my verilog-a code. I added a fixed delay of 500ps to DELAY, then it works. I am not sue I understand your question precisely, plz ask me if you are not asking this. |
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Title: Re: Problem of transition delay used in DTC verilog-A model Post by Geoffrey_Coram on Jan 5th, 2016, 11:34am In your previous post, you wrote: > I bounded the delay and it works! but just now you wrote: > I added a fixed delay of 500ps to DELAY, then it works. Which is it? For the first, I'd expect something like if (DELAY < 0) DELAY = 0; else if (DELAY > MAXDELAY) DELAY = MAXDELAY; whereas the second would be just DELAY = DELAY + 500p; In either case, what was the original value of DELAY computed from your formula? Code:
If V(DIN[i]) is between 0 and 1, then wouldn't DELAY be between 0 and 2047*tres? It doesn't seem like you'd need bounding -- unless V(DIN[i]) isn't between 0 and 1. |
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Title: Re: Problem of transition delay used in DTC verilog-A model Post by Ken Kundert on Jan 5th, 2016, 10:47pm It look like he is intending to convert the binary value of a bus to a delay value, but that is not what the following line does: Code:
He is multiplying the voltage of each bit line by a power of two, but he should apply a threshold before multiplying by the power of two: Code:
With his code, if V(DIN[10]) has overshoot and goes below zero, then the delay can go below zero. -Ken |
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Title: Re: Problem of transition delay used in DTC verilog-A model Post by Geoffrey_Coram on Jan 6th, 2016, 7:36am That's what I was trying to get him to consider -- not just blindly bounding the result or adding a fixed extra delay, but understanding where the problem comes from. That fixed extra delay might not be sufficient for other simulations. |
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Title: Re: Problem of transition delay used in DTC verilog-A model Post by Ken Kundert on Jan 6th, 2016, 9:04am Well it worked for me. I did not see the problem until your question. -Ken |
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Title: Re: Problem of transition delay used in DTC verilog-A model Post by Hamlee on Jan 7th, 2016, 3:33pm Dear Geoffrey, I think my last post is not correct. You are right, I added a 500ps delay to DALAY which make the error gone. But this is not the expected way the circuit should work. I corrected the code. Thanks for your question. It really made me think this question again. Code:
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Title: Re: Problem of transition delay used in DTC verilog-A model Post by Geoffrey_Coram on Jan 14th, 2016, 5:20am I think this is probably a significant improvement, only changing the value of DELAY when there's a crossing. It's much less likely that the DIN voltages will have strange values at those few crossing times. However, I think Ken's suggestion of using a threshold like (V(DIN[10] > vth) would still be a good idea, also. |
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