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Modeling >> Behavioral Models >> a error about the 'always' process of verilog-a
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Message started by Big Data on Jan 19^th, 2016, 8:06am

Title: a error about the 'always' process of verilog-a
Post by Big Data on Jan 19^th, 2016, 8:06am

does anyone know how to solve this error?(i'm using hspice2010):
pvaE* Not support Verilog-D syntax!!! 'always'
file "adc.va", line# 14
always @(posedge clk)begin

Title: Re: a error about the 'always' process of verilog-a
Post by Geoffrey_Coram on Jan 19^th, 2016, 10:04am

always is part of Verilog-AMS (or digital Verilog); it is not supported in Verilog-A.

You could try using the cross event

@(cross(V(clk) - vth)) begin

Title: Re: a error about the 'always' process of verilog-a
Post by AMS_ei on Aug 6^th, 2016, 7:43am

you can also use @(above(expr)) statement.

Thanks.