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Design Languages >> Verilog-AMS >> trancision filter warning in verilogA
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Message started by deltasigmaADC on Jan 27^th, 2016, 10:18pm

Title: trancision filter warning in verilogA
Post by deltasigmaADC on Jan 27^th, 2016, 10:18pm

I'm trying to implement sample and hold with finite rise and fall time unlike the the case in ahdlLib which has sudden jumps at output. My code is as below.

module sah_ideal_risefall(vin, vout, vclk);
input vin, vclk;
output vout;
electrical vin, vout, vclk;
parameter real vtrans_clk = 2.5;
parameter real risefalltime = 2p;
real vout_val;

analog begin
@(initial_step) begin
vout_val = 0;
end
@(cross(V(vclk) - vtrans_clk, +1)) begin
vout_val = V(vin);
end
V(vout) <+ transition(vout_val,0,risefalltime);
end
endmodule

During simulation spectre is giving me a warning as below.

line 22: Transition filter contains a continuous signal in the expression. Since a transition filter can only be applied to piecewise constant signals, redefine the expression to ensure that the transition filter applies only to a piecewise constant signal.

Isn't the variable updated only during positive edge of the clock? Doesn't that make the variable piecewise linear signal?

Thank you in advance

Title: Re: transision filter warning in verilogA
Post by Ken Kundert on Jan 28^th, 2016, 7:31pm

I believe you are correct, the warning seems wrong to me.

You don't need the initial_step() block. In varilog-A variables initialize to 0.

Please do not put language or simulator questions in the design boards.

-Ken

Title: Re: trancision filter warning in verilogA
Post by deltasigmaADC on Jan 28^th, 2016, 9:48pm

Thank you for the reply.

Sorry for posting in the wrong place.