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Design Languages >> Verilog-AMS >> Output for a pulse is just a DC voltage. Help!
https://designers-guide.org/forum/YaBB.pl?num=1454036563

Message started by Rosh on Jan 28^th, 2016, 7:02pm

Title: Output for a pulse is just a DC voltage. Help!
Post by Rosh on Jan 28^th, 2016, 7:02pm

Hello everyone,

Here is my code :

Code:

`include "disciplines.vams"

module allo(out);
parameter real td = 10n;
parameter real tt = 10n;
parameter real t1 = 0n;

output out;
voltage out;
real Vout, tend;

analog begin

@ (initial_step) begin
Vout = 0;

tend = $abstime + td; //return simulation time + td;
end

@(timer(tend))
Vout = 1.8;
V(out) <+ transition(Vout,0, td, tt);
end

endmodule

I expect to get a pulse with a finite rise and fall time. Instead i get this:

Title: Re: Output for a pulse is just a DC voltage. Help!
Post by deltasigmaADC on Jan 29^th, 2016, 2:58am

Your variable Vout is always assigned to 1.8. So you should be getting a DC at output, which is what you are seeing. Probably you wanted to update the variable to 0 at some point in time as well.

Cheers

Title: Re: Output for a pulse is just a DC voltage. Help!
Post by Geoffrey_Coram on Jan 29^th, 2016, 10:55am

Your indentation is confusing; it looks like the V(out) <+ transition is inside the @timer block.

Code:

analog begin
@ (initial_step) begin
Vout = 0;
tend = $abstime + td; //return simulation time + td;
end

@(timer(tend)) begin
Vout = 1.8;
end

V(out) <+ transition(Vout,0, td, tt);

end