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Design Languages >> Verilog-AMS >> phase wrapping, either 1 or 0 in VCO
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Message started by saralandry on Feb 5^th, 2016, 7:32pm

Title: phase wrapping, either 1 or 0 in VCO
Post by saralandry on Feb 5^th, 2016, 7:32pm

Hi

How can I have VCO with phase wrapping, either 1 or 0.
If I have Verilog-a model of VCO and I set fc (free running frequency) at 0 and Kvco at lets say 100e6, while the input voltage of the VCO is a pulse (between 0 and 1).
Does it mean that I have a vco with phase wrapping, either 1 or 0?

Thans for any help