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Design Languages >> Verilog-AMS >> Issues with a Differentiator in Verilog A
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Message started by Omnidroid on Apr 5^th, 2016, 3:46pm

Title: Issues with a Differentiator in Verilog A
Post by Omnidroid on Apr 5^th, 2016, 3:46pm

Hi Folks!

In order to obtain a derivative of an analog signal, if I use an ideal time derivative operator V(out) <+ ddt(V(in), there is a lot of noise observed at the output. I believe this is because this block does not have continuous states and the inability of the solver to take smaller steps causes the output to change rapidly.

Could anyone please suggest me a convenient option to eliminate this issue and yield a clean noiseless signal at the derivative output with adequate accuracy.

Thanks in advance! :)

Title: Re: Issues with a Differentiator in Verilog A
Post by Geoffrey_Coram on Apr 11^th, 2016, 9:29am

Perhaps you could connect a capacitor to the input, and then make the output proportional to the current into the capacitor. The capacitor should help the simulator choose good timepoints.