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Simulators >> AMS Simulators >> HOW TO DUMP STATES OF ALL FLIPFLOPS OF A DESIGN?
https://designers-guide.org/forum/YaBB.pl?num=1460122234

Message started by binod23 on Apr 8^th, 2016, 6:30am

Title: HOW TO DUMP STATES OF ALL FLIPFLOPS OF A DESIGN?
Post by binod23 on Apr 8^th, 2016, 6:30am

Dear All,

I want to record the states of all flipflops in the design as the verilog design is simulated for some fixed number of cycles. I don't have the need to view the waveforms of those signals. I want to use those states for further processing. Please tell how to dump the states of the flipflops corresponding to each simulation cycle ? I am ready to use any simulator --vcs/ncsim/modelsim/icarus verilog.

I doubt if the vcd file which is generated would serve my purpose as I don't know any method to open vcd files except gtkwave that I don't want (as waveforms are not needed).

Please help. It is urgent.

Thanks In Advance

Title: Re: HOW TO DUMP STATES OF ALL FLIPFLOPS OF A DESIGN?
Post by Geoffrey_Coram on Apr 21^st, 2016, 12:51pm

This probably should have been posted in "AMS Simulators" instead.