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Simulators >> RF Simulators >> How to reduce/eliminate PSS convergence errors?
https://designers-guide.org/forum/YaBB.pl?num=1460240698

Message started by iVenky on Apr 9^th, 2016, 3:24pm

Title: How to reduce/eliminate PSS convergence errors?
Post by iVenky on Apr 9^th, 2016, 3:24pm

Hi,

I am running PSS on Cadence Virtuoso for a wide-range Quadrature VCO. I am facing convergence issues sometimes. Sometimes it works. Do you know the reason behind these convergence issues and how to reduce/solve those?

Title: Re: How to reduce/eliminate PSS convergence errors?
Post by ULPAnalog on Apr 9^th, 2016, 3:51pm

Increasing tstab, adding cmin helps convergence. Also if you are using verilog A models, they should not contain hidden states. A more general discussion on convergence issues can be found here
http://www.designers-guide.org/Forum/YaBB.pl?num=1208694646/1#1