The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> global parameters in Verilog-A?
https://designers-guide.org/forum/YaBB.pl?num=1460478215

Message started by danmc on Apr 12^th, 2016, 9:23am

Title: global parameters in Verilog-A?
Post by danmc on Apr 12^th, 2016, 9:23am

Is there a way for a Verilog-A and/or Verilog-AMS module to be able to access a global design parameter? Is the only way to pass it as an instance parameter to the module?

Thanks
-Dan

Title: Re: global parameters in Verilog-A?
Post by cheap_salary on Apr 12^th, 2016, 7:34pm

Use Macros.

Macro's value can be passed by simulator command option.

For example,
spectre -va,define MACRO=value