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Design Languages >> Verilog-AMS >> Pulse generator for an oscillator in Verilog-A
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Message started by Omnidroid on Apr 19^th, 2016, 1:52am

Title: Pulse generator for an oscillator in Verilog-A
Post by Omnidroid on Apr 19^th, 2016, 1:52am

Hello Everyone,

I'm trying to model a fixed pulse generator for an oscillator that would look at an input signal and if the amplitude is below a certain threshold and the system state is 0, then the state is assigned 1. Also, if the amplitude of the input signal is above a certain threshold and the system state is 1, then the state is assigned 0 . A minimum and maximum time is also required to be specified to remain in each state, so neither the system is continuously switching nor stays in one state forever.

In order to satisfy the above conditions, I have written the following code, however, I am unsure how to specify the minimum and max. time to remain in each state due to which the system stays in the same state forever.

---------------------------------------------------------------------------
// VerilogA for psensor, autosw, veriloga
`include "constants.vams"
`include "disciplines.vams"
module autosw(in, out);
input in;
output out;
voltage in, out;
parameter real td = 1.3375m;                    //Width of the pulse
parameter real tt = 1n;                         //Output transition time
parameter real startval = 0;                    //Low Voltage level
parameter real endval = 2.5;                    //High Voltage level
parameter real vthmin = 1.182m from (0:inf);    //Min. voltage from input afterwhich system should be closed [V]
parameter real vthmax = 97.32m from (0:inf);    //Max. voltage from input after
which system should be open [V]
real Vout, tend, rst;
integer state;
analog begin
    @(initial_step) begin
      Vout = startval;
      tend = $abstime + td;           //Return simulation time + Td;
    end
   @(cross(V(in) vthmin, -1)) begin
     state = 1;
     Vout = endval;
   end
  @(cross(V(in) vthmax, 1)) begin
     state = 0;
     Vout = startval;
   end
  @(timer(tend)) begin
   Vout = endval;
  end

V(out) <+ transition(Vout, 5n, 1n);

end
endmodule
------------------------------------------------------------------------------------------------------

Looking forward to your needful comments,

Thanks in advance,

Saoni

Title: Re: Pulse generator for an oscillator in Verilog-A
Post by boe on Apr 20^th, 2016, 2:16am

Saoni,

Omnidroid wrote on Apr 19^th, 2016, 1:52am:

You could set a time 'tend_max' in the cross event blocks. Then you can use a timer event on 'tend_max' to end the pulse.
- B O E

Title: Re: Pulse generator for an oscillator in Verilog-A
Post by Omnidroid on Apr 26^th, 2016, 2:29am

Hi B O E,

Thank you for your reply! I have implemented the concept you have mentioned, however, it doesn't fulfil the purpose.

I would explain the concept and the code I have written underneath:
-----------------------------------------------------------------------------------------------------
The purpose of the block is:

1. To change the state to 0 or 1 if the input is detected to be vthmax (Maximum threshold) or vthmin (Minimum threshold) at rising and falling edges respectively.

2. In case, the input reaches the maximum of minimum thresholds too FAST, it should wait for a minimum time "Tmin" before changing the respective states.

3. In case, the input reaches the maximum and minimum thresholds too SLOW, the states should be changed after a time "Tmax" after the last crossing event.

In order to fulfil the above conditions, I have written this code:
-----------------------------------------------------------------------------------------------------------

Code:

`include "constants.vams"
`include "disciplines.vams"
module autoswitch(in, out);
input in;
output out;
voltage in, out;
parameter real tmin = 20u;   //Minimum time before the state changes its
transition
parameter real tmax = 20u;
parameter real tt = 1n;     //Output transition time
parameter real startval = 0;  //Low Voltage level
parameter real endval = 2.5;   //High Voltage level
parameter real vthmin = 1.182m from (inf :inf);    //Min. voltage from input should be closed [V]
parameter real vthmax = 97.32m from (inf:inf);   //Max. voltage from input after which system should be open [V]

real vout, tstartrise, tstoprise, tstartfall, tstopfall, crossrise, crossfall;
integer state, state_d, crossing;
analog begin
@(initial_step) begin
      vout       = 0;
      state      = 0;
      state_d    = 0;
      tstoprise  = 0;
      tstartrise = 0;
      tstartfall = 0;
      tstopfall  = 0;
      crossing   = 0;
      crossrise  = 0;
      crossfall  = 0;
   end

   state_d = transition(state, tmin, 1n);      // Generating a replica of the output signal delayed by tmin units for comparison of thresholds
  @(cross(V(in) vthmin, 1)) begin
$strobe("Falling edge detected. Change state to 1. \n abs_time=%g", $abstime);
     crossrise = $abstime;
    if (state_d == 1) begin //Change the state
       crossing = 1;
       vout     = endval;
       state    = 1;
   $strobe("Falling edge detected. Change state to 1. \n abs_time=%g",$abstime);
    tstartrise = $abstime;
    tstoprise =  tstartrise +tmax;
    end
    else begin
   if (state_d == 0) begin //Resume state
       crossing = 0;
       vout     = startval;
       state    = 0;
    $strobe("Resume low state");
     end
    end
   end
@(timer(tstoprise)) begin //At "tstoprise" after every falling edge event, if threshold is less than vthmin, resume state else change the state
  tstoprise = tstartfall;
  if (V(in) > vthmin)  begin
        crossing = 1;
        vout = startval;
        state = 0;
    end
  end

@(cross(V(in) vthmax, 1)) begin

$strobe("Rising edge detected. Change state to 1. \n abs_time=%g", $abstime);
     crossfall = $abstime;
    if (state_d == 0) begin
       crossing = 1;
       state = 0;
       vout = startval;
$strobe("Rising edge detected. Change state to 0.  \n abs_time=%g", $abstime);
   tstartfall = $abstime;
   tstopfall  = tstartfall +tmax;
   end
   else begin
   if (state_d == 1) begin
       crossing = 0;
       vout     = endval;
       state    = 1;
       $strobe("Resume high state");
     end
   end
  end

@(timer(tstopfall)) begin
  tstopfall = tstartrise;
   if (V(in) < vthmax) begin
        crossing = 1;
        vout = endval;
        state = 1;
  end
end

V(out) <+ transition(vout, 5n, 1n);
end
endmodule

---------------------------------------------------------------------------------------------------------------
I would be grateful to know if the above conditions would be fulfilled by the following code.

Kind Regards,

Omnidroid

Title: Re: Pulse generator for an oscillator in Verilog-A
Post by Geoffrey_Coram on Apr 26^th, 2016, 6:46am

I'm not sure all simulators allow you to do this:
state_d = transition(state, tmin, 1n);

I'd suggest creating a new node, and set
I(state_d) <+ transition(state, tmin, 1n);
I(state_d) <+ V(state_d); // 1-Ohm resistor
then use V(state_d) instead of the variable state_d.

Also, this is a bad idea:
if (state_d == 1) begin
because it's always a bad idea to test equal (==) with a floating-point number. state_d could be 1.00000000000000001 or 0.9999999999584 or something, and the test will fail.

Title: Re: Pulse generator for an oscillator in Verilog-A
Post by Geoffrey_Coram on Apr 26^th, 2016, 6:48am

It would also be a lot easier to make any sense of your code if you would use the "code" tag (use the button with a # from the set of buttons above the message box). Then you can fix the indentation properly.

Title: Re: Pulse generator for an oscillator in Verilog-A
Post by Forum Administrator on Apr 30^th, 2016, 1:30am

Geoffrey,
Are you serious? There is a simulator out that does not support assigning the output of a transition function to a local variable like this ...

Code:

state_d = transition(state, tmin, 1n);

Frankly, I am shocked. That seems pretty lame.

-Ken