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Design Languages >> Verilog-AMS >> Stopping HSPICE from within Verilog-A
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Message started by AA on Apr 25^th, 2016, 1:43pm

Title: Stopping HSPICE from within Verilog-A
Post by AA on Apr 25^th, 2016, 1:43pm

Hello everyone!

Is there a way to dynamically stop HSPICE simulation (including sweeping) from within a verilog-a module?

For example, we perform a very long transient analysis like this:

Code:

.tran 0.1n 50u sweep monte=50

And in our verilog-a module, if a condition is satisfied, we need to stop the simulation (including sweeping). For example:

Code:

if (state==done_state) begin
// I would like to stop hspice here
// there must be a command in verilog-a that is
// similar to $finish() in digital verilog
// Anyone please?
end

My HSPICE version is 2013.03-SP2.

Thank you.

Title: Re: Stopping HSPICE from within Verilog-A
Post by Geoffrey_Coram on Apr 26^th, 2016, 6:41am

The Verilog-A language provides $finish and $stop; you can try those and see if they work for what you want to do.