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Simulators >> RF Simulators >> VerilogA and PSS convergence issue
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Message started by deltasigmaADC on Apr 27^th, 2016, 10:08pm

Title: VerilogA and PSS convergence issue
Post by deltasigmaADC on Apr 27^th, 2016, 10:08pm

Hi all,

I've a CTDSM circuit which I'm simulating. To get the Signal Transfer Function(STF) I've earlier used pss and pac. It worked when my model circuit had only analogLib elements.

Later I've changed the flash and DACs to verilogA. This was to add few more functions easily and model some nonideality easily. But after this pss seems to have a great difficulty in converging. Even if it converges it's giving wrong results.

The verilogA models that I've written don't have any convergence issues in transient. Any possible discontinuity has been handled using transition filters. Transient runs with any warnings and results are right.

Has anyone faced issues with verilogA models while doing RF analysis? If you did, do you know any easy way to get around this issue?

Title: Re: VerilogA and PSS convergence issue
Post by cheap_salary on Apr 28^th, 2016, 5:17am

deltasigmaADC wrote on Apr 27^th, 2016, 10:08pm:

I've a CTDSM circuit which I'm simulating.
To get the Signal Transfer Function(STF) I've earlier used pss and pac.
It worked when my model circuit had only analogLib elements.

In CTDSM, you have to evaluate L0c(s) and L1(z).
How do you simulate L1(z) ?

L0c(s) can be evaluated easily by conventional AC analysis or PSS/PAC of sideband=0.
However we have to use Ideal-Sample-Hold for evaluating L1(z).
Here Ideal-Sample-Hold is for emulating NRZ-DAC with no quantization.
You have to realize this Ideal-Sample-Hold by combination of ideal-switch and capacitor, since we can not use PSS if hidden states are included in Sample-Hold model.

If your DAC is current type, map output voltage of Ideal-SH to current by VCCS.

deltasigmaADC wrote on Apr 27^th, 2016, 10:08pm:

Later I've changed the flash and DACs to verilogA.

How do you apply PAC for multi-level Quantizer ?
PAC is no more than small signal analysis.

Title: Re: VerilogA and PSS convergence issue
Post by Ken Kundert on Apr 28^th, 2016, 11:36am

ΔΣ modulators do not have a periodic response, and so you cannot use PSS analysis. If you tried, you would get convergence issues.

-Ken

Title: Re: VerilogA and PSS convergence issue
Post by cheap_salary on Apr 28^th, 2016, 9:38pm

Ken Kundert wrote on Apr 28^th, 2016, 11:36am:

ΔΣ modulators do not have a periodic response, and so you cannot use PSS analysis.

For evaluation of NTF and STF, close loop operation is not required.
So we can use PSS/PAC for evaluation of NTF and STF.
Attached figure shows NTF and STF of SC-DSM-ADC.

Title: Re: VerilogA and PSS convergence issue
Post by cheap_salary on Apr 28^th, 2016, 9:44pm

We can evaluate NTF and STF by using PSS/PAC, as far as we ignore quantization of DAC.
This is true for CT-DSM-ADC as well as SC-DSM-ADC.

However we can not apply PSS/PAC, if we include quantization of DAC, that is, multi-level DAC.
This is critical issue especially for evaluation of NTF in CT-DSM-ADC, since nonidealities of DAC affects NTF severely in CT-DSM-ADC.

Title: Re: VerilogA and PSS convergence issue
Post by cheap_salary on Apr 28^th, 2016, 9:49pm

cheap_salary wrote on Apr 28^th, 2016, 9:38pm:

Ken Kundert wrote on Apr 28^th, 2016, 11:36am:

ΔΣ modulators do not have a periodic response, and so you cannot use PSS analysis.

For evaluation of NTF and STF, close loop operation is not required.
So we can use PSS/PAC for evaluation of NTF and STF.
Attached figure shows NTF and STF of SC-DSM-ADC.

I request Administrator to delete this post

Title: Re: VerilogA and PSS convergence issue
Post by deltasigmaADC on Apr 29^th, 2016, 3:12am

Hi all,

Thank you for your reply.

Ken, I think only when quantization noise is considered in the modulator, it becomes non periodic because of the random nature of the noise. Since I was interested in STF I took quatizer out of picture. Then the system becomes LPTV. For this I've replaced the quantizer by sample and hold followed by VCCS. No quatization operation if performed on the sampled data.

If I use switches and caps to implement the sample and hold, VCCS for DAC, I'm able to get the STF and signal component at loopfilter integrator outputs. Problem comes when I use some verilogA blocks to implement the SAH or replacing the VCCS. I still couldn't figure out why verilogA is giving me wrong result. Could it be because for verilogA blocks it's hard to build a small signal model? Does PSS need a small signal model of the circuit for simulation? Until now I was under the impression it doesn't need one. Only PAC need small signal model.

cheap_salary, for getting NTF i usually get the closed loop impulse response and take FFT of it. Again for this I won't use a quantizer. Since CTDSM therory itself is built on assuming the quantizer to be an additive noise source I think we can eliminate this nonlinear block when ever needed. Of course if you are interested in SQNR then transient simulation need to be done with quantizer.
I found it helpful to use closed loop response for getting NTF and STF than open loop since it was giving me more accurate results.

Title: Re: VerilogA and PSS convergence issue
Post by cheap_salary on Apr 29^th, 2016, 4:20am

deltasigmaADC wrote on Apr 29^th, 2016, 3:12am:

Problem comes when I use some verilogA blocks to implement the SAH or replacing the VCCS.
I still couldn't figure out why verilogA is giving me wrong result.

Show me Verilog-A code of SAH.
I think your Verilog-A model has hidden states.
However you specify "(* instrument_module *)" or "(* ignore_state *)" in it.

See http://www.designers-guide.org/Analysis/hidden-state.pdf
Compare the following two models.
http://www.designers-guide.org/VerilogAMS/functional-blocks/sh/sh.va
http://www.designers-guide.org/VerilogAMS/rf-models/sh/sh.va

deltasigmaADC wrote on Apr 29^th, 2016, 3:12am:

for getting NTF i usually get the closed loop impulse response and take FFT of it.

Do you mean broad band white spectrum drive instead of single-tone drive ?

V(z) = STF(s)*U(s) + NTF(z)*E(z)

For evaluation of STF, U(s)=1, E(z)=0.
For evaluation of NTF, U(s)=0, E(z)=1.
Right ?

deltasigmaADC wrote on Apr 29^th, 2016, 3:12am:

I found it helpful to use closed loop response for getting NTF and STF than open loop since it was giving me more accurate results.

I don't think so.
As far as we can not reflect actual waveform of DAC, both NTF and STF are far different from actual situation.
So close loop simulation is too expensive for evaluation of NTF and STF, if you use Sample-Hold circuit(Zero-Order-Hold) instead actual DAC.

BTW, I don't use PSS/PAC for designing CT-DSM-ADC at all.
I use only Transient Analysis with sweeping frequency of single-tone.
Or with two tones drive.