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Design Languages >> Verilog-AMS >> Use of ddx in Verilog-A
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Message started by Sitansu on Apr 27^th, 2016, 10:57pm

Title: Use of ddx in Verilog-A
Post by Sitansu on Apr 27^th, 2016, 10:57pm

In my model, charge of a nonlinear capacitor is given as Q=f(V2,V3)*Vc where V2, V3 are terminal or bias voltages and Vc is the voltage across capacitor. Current through capacitor can be given as I=ddt(Q). Can I also write I=ddx(Q,V2)*ddt(V2)+ddx(Q,V3)*ddt(V3)+f(V2,V3)*ddt(Vc)?
Whenever I am replacing 1st expression by the second expression, my AC results matches but transient result do not match. Is it wrong to use ddx or is there any restriction in verilog-a for using ddx?

Title: Re: Use of ddx in Verilog-A
Post by Ken Kundert on Apr 28^th, 2016, 11:32am

Your equations are correct in a differential equation sense, but they are inaccurate in a finite-difference sense. Transient analysis uses finite-differences to approximate derivatives. Your second equation is only approximate when using finite differences. You should not use it.

Also, I suspect that first equation is also wrong. It is certainly wrong if you believe f represents the capacitance. I recommend that you read Modeling Varactors.

-Ken

Title: Re: Use of ddx in Verilog-A
Post by Sitansu on Apr 28^th, 2016, 9:47pm

Thank you Ken,

I might have written Q=c*V here, but in verilog I am not writing it as I=c*ddt(V). I always use I=ddt(Q). So in reality there is nothing like C in my equation. I just use the word capacitor for easy communication.