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Design >> Analog Design >> Delay Lines for Calibrating Sampling Clocks
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Message started by DanielLam on Apr 29^th, 2016, 11:33pm

Title: Delay Lines for Calibrating Sampling Clocks
Post by DanielLam on Apr 29^th, 2016, 11:33pm

Hi everybody,

I've been doing a literature search on delay lines for sampling clocks, and there seems to be two main contenders.

1) Current-starved inverters
2) Adding caps onto inverter outputs

Which is more preferable for delay lines for sampling clocks? I am not talking about VCOs where current-starved inverters are prevalent.

I am leaning towards the capacitors as I assume they have less jitter from the supply rails. I am just wondering about other peoples' thoughts.

Thanks,
Daniel Lam