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Design >> RF Design >> Output buffers for an LC VCO
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Message started by iVenky on Apr 30^th, 2016, 10:50am

Title: Output buffers for an LC VCO
Post by iVenky on Apr 30^th, 2016, 10:50am

Hi! I am designing an LC VCO and would want to design output buffers for driving the output for testing. What's the general architecture for the output buffers? Can it be differential? I have seen some architectures where they use class A amplifier but I would like to know what is used generally.

Thanks!

Title: Re: Output buffers for an LC VCO
Post by raja.cedt on Apr 30^th, 2016, 1:17pm

Diff pair with LC tuned load.

Title: Re: Output buffers for an LC VCO
Post by rfmagic on May 25^th, 2016, 2:03pm

It really depends on the operating frequency but a good choice would be a series of push-pull (inverting stage) stages. This way you make sure the signal is rail-to-rail. on the other hand you get a a square wave with high harmonic content. so unless you need a clean sine wave, I would choose the inverting stages.
It works fine for me up to 15GHz in 65nm CMOS

Title: Re: Output buffers for an LC VCO
Post by raja.cedt on May 30^th, 2016, 1:54pm

Dear rfic-
I would go with inverting stage if I have to buffer it internally like clock tree fashion, but if you have to bring it out and test-it with for a process maturity info or in case test-chip, you might be having some troubles with 50ohm. That's why Generally people tend to go cml buffer or a open drain structure. Correct me if I am wrong.

Best Regards,
Raj.

Title: Re: Output buffers for an LC VCO
Post by rfmagic on Jun 15^th, 2016, 1:27pm

@ raja
I agree with your argument. I probably missed the point that this buffer should be used for low impedance load for testing.
Thanks for your correction