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Design >> RF Design >> ESD failure mechanism
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Message started by raja.cedt on May 9^th, 2016, 5:05am

Title: ESD failure mechanism
Post by raja.cedt on May 9^th, 2016, 5:05am

Dear all-
I read in some papers that "HBM failure only cases Thermal failure and CDM causes mainly gate Oxide failure". Can any one please explain a bit more like what is thermal failure (means junction damage or metal damage--)

Also can any one kindly give me any good reference about failure mechanism?

Best Regards,
Raj.

Title: Re: ESD failure mechanism
Post by loose-electron on May 24^th, 2016, 6:28pm

HBM model can cause oxide failure as well. Because the source is resistive in the HBM, generally a higher ESD voltage is tolerable. (In effect you get voltage division between the HBM resistance and victim DUT impedance.)

Two things cause ESD failures:

Overvoltage (generally leading to gate oxide failures)
Overcurrent (due to the brief but multiampere inrush current)

I suspect the overcurrent failure is what they refer to as "thermal failure"

Title: Re: ESD failure mechanism
Post by raja.cedt on May 31^st, 2016, 1:03am

Hi-Thanks for the info. Means we can't distinguish based on CDM or HBM only based on current high voltage or high current, is this correct?

Slightly different questions:
1. I am aware of diodes from signal bumps to both rails and resister in series. Generally resister is to limit the current, means it will be effective mainly for CDM and not much effective for HBM event because of 1.5K series resistance, am I correct??
2. People call diodes on I/O bumps as HBM diodes, means are they are not effective for CDM event, if so why?

Again, are you aware of any detailed public document about ESD basics (not simply what is HBM and CDM) with bit of explanation.

Many Thanks,
Raj.

Title: Re: ESD failure mechanism
Post by loose-electron on May 31^st, 2016, 1:37pm

There is a basic book on the subject:

"Basic ESD and I/O Design by Dabral and Maloney (Wiley Interscience ISBN 0-471-25359-6, 1998)

I have a copy but it's a bit out of date.

Suggestion - put together some simulation models for machine and HBM sources, and also model some I/O cells and their diode structures. Looking at what happens during the transient simulations is informative.

Make sure you include parasitic resistances and real diode models (not ideal) and you can learn a lot from that.

http://electronicdesign.com/power/protect-your-fortress-esd

Give that a read too - written from the perspective of PCB level design but still useful. I wrote that not too far back.