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Design >> High-Speed I/O Design >> 3.3 v decap using 1.8 volt tolerant mos decaps without using MOM
https://designers-guide.org/forum/YaBB.pl?num=1462798387

Message started by radioelectra on May 9^th, 2016, 5:53am

Title: 3.3 v decap using 1.8 volt tolerant mos decaps without using MOM
Post by radioelectra on May 9^th, 2016, 5:53am

Hi all,

In order to increase the capacitance density instead of using MOM, can we build decap with 1.8 volt tolerant MOS transistor?

The structure will be pmos transistor three terminals (source, drain, bulk) tied vcco and gate tied to vcco/2 where vcco/2 derived from resistive divider circuit.

What are the issues with above topology

Title: Re: 3.3 v decap using 1.8 volt tolerant mos decaps without using MOM
Post by raja.cedt on May 10^th, 2016, 12:31am

Yes you can, that's very common as long as leakage doesn't hit your spurs. Didn't get you about why do you need potential divider. generally one side connected to vco and another side go's to Charge pump.

Best Regards,
Raj.