The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> Bondwire Inductance & Pad Cap Modelling
https://designers-guide.org/forum/YaBB.pl?num=1467214431

Message started by jdp on Jun 29^th, 2016, 8:33am

Title: Bondwire Inductance & Pad Cap Modelling
Post by jdp on Jun 29^th, 2016, 8:33am

Hi,

I want to model the Bondwire Inductance & Pad Capacitance that come to the picture when connecting Vdd, Gnd etc. from outside the IC. Presently, I am simulating my circuit (switched capacitor one) with a model as seen in attached schematic. Is this model okay to use?

Problem faced is that the internal supply rail voltages are RINGING - and decoupling capacitors are of no help as the Vdd & corresponding Gnd are oscillating in phase..!

Please suggest how to get rid of such ringing on internal supply rails.

Title: Re: Bondwire Inductance & Pad Cap Modelling
Post by Ken Kundert on Jun 29^th, 2016, 9:10am

http://www.designers-guide.org/Design/bypassing.pdf

Title: Re: Bondwire Inductance & Pad Cap Modelling
Post by raja.cedt on Jun 30^th, 2016, 2:19am

Hi-
1. Bond wire model you should get it from packing people, as a rule of thumb use 1nH/1mm with some seris resistance. I guess you have double bond, but please some mutual inductance also (~0.6).
2. Always do an Em sim for pad capacitance or calculate from metal cap density from foundry
3. . Add a small series resistance to the decap, Just add enough if it is more than enough decap is no more decap rather it is a resister, which will compromise supply noise.

This is the reason why always foundries makes decap std cells with non minimal length.

Best regards,
Raj.

Title: Re: Bondwire Inductance & Pad Cap Modelling
Post by jdp on Jun 30^th, 2016, 8:03am

Thanks Ken, and Raja!

Raja, one thing if you may please help me with.
I am attaching a MUTUAL INDUCTANCE model for my bondwires (as suggested by you). Can you please check if it's okay? (as I couldn't get much reference on the web regarding usage of "mind"), also if the inductor DOT SIGNs are properly placed?

Title: Re: Bondwire Inductance & Pad Cap Modelling
Post by raja.cedt on Jun 30^th, 2016, 3:48pm

yah--double bond always will have +ve mutual coupling. If you want to enhance your understanding,may be the following book might be a good start.

Electromagnetics for High-Speed Analog and Digital Communication Circuits

Title: Re: Bondwire Inductance & Pad Cap Modelling
Post by jdp on Jun 30^th, 2016, 7:56pm

So, in my previous schematic, I should add mutual coupling between ALL the inductors, right? Is a coupling coeff ~ 0.6 ok for all of them on average.

Also, Thanks for sharing the book...

Title: Re: Bondwire Inductance & Pad Cap Modelling
Post by loose-electron on Jul 6^th, 2016, 10:33pm

what is the package? does a package and bonding model exist?

Title: Re: Bondwire Inductance & Pad Cap Modelling
Post by jdp on Jul 7^th, 2016, 1:05am

Hi loose-electron,

Right now, I don't have any idea of what package I will use...

I just want to gauge how my designed ckt might behave in the actual environment of pads & bondwires..and put in place some precautionary measure (like using a damping resistor in series with decoupling cap to reduce ringing in the supply lines) if possible!

But, in the absence of a precise package and bonding model, is it anyway useful to design and use such damping resistors based on just an approx. model? :-?

Title: Re: Bondwire Inductance & Pad Cap Modelling
Post by loose-electron on Jul 8^th, 2016, 11:48pm

Your internal model includes no C inside the chip, thus the extreme ringing.

Often under 100MHz you can design without the package model and survive.

Otherwise target some plausible packages for the chip and get a suitable model to start with

Title: Re: Bondwire Inductance & Pad Cap Modelling
Post by jdp on Jul 9^th, 2016, 1:50am

Thank you so much Jerry for sharing insight from your experience :) it is really helpful information..!

If you don't mind my naivety, can you please elaborate a little on what you mean by "...internal model includes no C inside the chip" - what Cap (and between what) are you referring to?

Title: Re: Bondwire Inductance & Pad Cap Modelling
Post by loose-electron on Jul 17^th, 2016, 9:41am

jdp wrote on Jul 9^th, 2016, 1:50am:

Internal capacitance from power to ground