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Design Languages >> Verilog-AMS >> using branch as a pass-through to measure current of DUT
https://designers-guide.org/forum/YaBB.pl?num=1467843989

Message started by va_user on Jul 6^th, 2016, 3:26pm

Title: using branch as a pass-through to measure current of DUT
Post by va_user on Jul 6^th, 2016, 3:26pm

I have a device under test (DUT) and want to use a verilog-A module to monitor the current through the DUT and take actions based on that. Can I not use a verilog-A module as a pass-through like so:

Code:

`include "discipline.h"
`include "constants.h"

module current_meas(vss_pos, vss_neg);

input vss_pos;
output vss_neg;

electrical vss_pos;
electrical vss_neg;

branch (vss_pos, vss_neg) input_branch;

analog begin

I(vss_pos) <+ I(vss_neg);
V(vss_pos) <+ V(vss_neg);

end

endmodule

I connected this VA module in series between the DUT and a 0V DC supply (VSS) to node 0.

When I do this, the spice simulation runs to completion but when I look at the waveform of the current through the VSS supply it is 0. I do get non-zero current through the VDD supply connected to the DUT in the spice waveform, but the value does not match what I get when I run the same simulation without the VA module.

I assume I cannot simply use a branch statement as a pass-through (i.e. short circuit) as I have done above?

Title: Re: using branch as a pass-through to measure current of DUT
Post by Ken Kundert on Jul 6^th, 2016, 7:10pm

No you cannot. You cannot assign both the voltage and the current of a branch. In Verilog-A branches are either voltage or current sources, and you specify the voltage or current of the source. In your model you are trying to make the same branch both a voltage and a current source. That is impossible.

Instead, model a short (0-volt voltage source) between the two nodes, like this ...

Code:

module current_probe(p, n);
electrical p, n;
branch (p, n) short;

analog V(short) <+ 0;
endmodule

Or like this ...

Code:

module current_probe(p, n);
electrical p, n;
analog V(p,n) <+ 0;
endmodule

You seem to have the wrong mental model for Verilog-A. To understand it better, you might want to take a look at this Verilog-A tutorial.

Thanks for providing a simple model and providing the whole model. It makes it much easier to understand what is going on.

-Ken

Title: Re: using branch as a pass-through to measure current of DUT
Post by va_user on Jul 7^th, 2016, 9:23am

Thanks, that works. One thing I noticed is that the VSS current waveform of the simulation using the VA module you listed is 7.28% higher than the same current waveform when not using the VA module. In theory a short circuit in the VA module should not affect the current through the DUT.

Is there some loss of precision that is occurring due to the current calculations performed by the VA module?

Title: Re: using branch as a pass-through to measure current of DUT
Post by Ken Kundert on Jul 8^th, 2016, 10:12am

The result should be identical to what you would measure if you used a 0V voltage source to measure current, so there is no approximation. Perhaps the approximation is in the way you are measuring current without the Verilog-A module.

-Ken

Title: Re: using branch as a pass-through to measure current of DUT
Post by Geoffrey_Coram on Jul 14^th, 2016, 12:44pm

Ken -
You have an extra close-paren ) in your code:

Code:

analog V(p,n) <+ 0);

Title: Re: using branch as a pass-through to measure current of DUT
Post by Ken Kundert on Jul 14^th, 2016, 11:16pm

Whoops. Thanks. I have now fixed it.

-Ken