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Design Languages >> Verilog-AMS >> Testbenching with mixed signals? WREAL
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Message started by Jelena on Jul 20^th, 2016, 8:06am

Title: Testbenching with mixed signals? WREAL
Post by Jelena on Jul 20^th, 2016, 8:06am

Hi all,

I am having trouble writing a model in Verilog-AMS using wreal types.
It's a model of a PLL and I was given a huge testbench that was made for the transistor level design, etc. ...

anyway, I am still a newbie and for starters I just want to check the values of the ports I am trying to use...

The PLL uses fractional N divider block and I wanted to make use of the signals to build the output of the feedback loop...

The equation for output frequency consists of 30-bit input signals and 7-bit input signals.
I am having trouble defining them and driving them in my testbench to test if the values are handled correctly in the buses.

This is what I did (conceptually):

module fracN_div(in, out, dig1, dig2)
input wreal in;
real rin;
input dig1, dig2;
wire [7:0] dig1;
wire [29:0] dig2;

...
...
endmodule

making a schematic testbench in AMS Designer (virtuoso), how can I define the bits of the dig1 and dig2 to be made of digital signals?
I tried hooking them up to a vdc of 1.1V input (the specified input of signals) for logic 1 and hooked them to gnd for logic 0, but when I check the wire values using $display I get weird outputs (00000x0 or 0)
(I have connected them so that it should read 7'b2 )
I tried stating them as logic but that is by default in verilog-ams and it didn't help...

can someone help?

Title: Re: Testbenching with mixed signals? WREAL
Post by Ken Kundert on Jul 24^th, 2016, 12:47am

The code you gave looks okay, and seems unlikely to result in the output you are describing. However, it is difficult to identify the issue because you describe it in vague terms. With languages, the details are important. It is better to give the code and quote the result than it is to give a verbal description.

In this case you are trying to describe logic signals with real numbers. This conversion involves connect modules. You should describe those as well.

-Ken

Title: Re: Testbenching with mixed signals? WREAL
Post by Jelena on Aug 16^th, 2016, 8:15am

I am sorry, I thought I would get a mail if there was a reply!

Anyways,

since I am a noob at AMS Designer, I discovered that the testbench was wrong.
the problem was defining analog input signals and treating them as logical in the code.
What I did was set the vdc generators in the testbench schematic to be 1.1V for logical 1 and the Connect Rule was designed for 1.8V. so that produced an error.

Changing the rule to be correct or the voltage level of the logical 1 in the vdc solved the problem.

Thank you so much Ken for replying!