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Simulators >> AMS Simulators >> Problem with simulating AMS test bench
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Message started by Sherif on Aug 1^st, 2016, 8:05am

Title: Problem with simulating AMS test bench
Post by Sherif on Aug 1^st, 2016, 8:05am

Hey all,

I'm trying to run a simulation for a verilogAMS test bench using ADE XL. The design unit is set to config, which I use to configure the instantiations of the cells in my test bench, here I'm using two cells of the same name one schematic and the other one is veriloga but in two different libraries. The instantiation through the config file works properly but when I run the simulation I get the following message error:

ncelab: *F,OSDINF (#path/verilogams/verilog.vams,51|9): instance 'verilogamsTest.dutsch' of design unit 'XYZ' is a leaf instance and is unresolved in cellview 'libTest.verilogamsTest:verilogams'. Ensure that the design unit is either pre-compiled or its corresponding text file is specified for compilation. Also, check the binding for this instnce in Cadence Hierarchy Editor to confirm if it is set to externalHDL or addStopPoint or if nlAction is set to 'stop' for the specified instance.

I have to say that I do not even understand what is trying to say with this error message let alone figure out the problem!!

My Global bindings in my config file are as follows:
Library List: contains the libraries of the two instantiated cells in the verilogams file
View List: schematic symbol veriloga
Stop List: schematic symbol veriloga

I would be very thankful for any help!!
Sherif

Title: Re: Problem with simulating AMS test bench
Post by AMS_ei on Jan 18^th, 2017, 7:32am

Hi,

Could you please check your verilogams view has been created properly?
If not, can you please re-create the verilogams view. I think the issue is with the verilog ams view itself.

Thank you.

Kind regards,